The entire chip achieves systematic fault integrity of ASIL-D/SIL-3. The random fault metric integrity of each respective domain assumes that sufficient hardware diagnostics are used in conjunction with recommended software/system diagnostics and assumptions of use (AoU) are implemented.

MCU Island: Jacinto 7 family of products integrates a safety MCU inside the SoC to perform monitoring of safety critical functions and signals. This is referred to as the MCU island and is shown in the block diagram above in green. The MCU island provides a safety partition with sufficient hardware diagnostics in place to achieve random fault integrity of ASIL-D/SIL-3. It is comprised of a pair of R5F cores which can be operated in lockstep, safe interconnects for intra-domain communication, as well as a diverse set of peripherals.

Extended MCU Island: On some devices within the Jacinto 7 family (please see Table 1: Safety Scalability Table) an extended MCU island is present. This partition is shown in green in the block diagram above and increases ASIL-D/SIL-3 performance with additional R5F core(s) for increased ASIL-D/SIL-3 DMIPS as well as additional instances of peripherals that can achieve random fault integrity of ASIL-D/SIL-3. The extended MCU also enables up to ASIL-D/SIL-3 access to DDR, which is beneficial if safe data access is required and on-chip memory within the safety island or extended safety island is not sufficient.

The rest of the SOC (main domain as show in the grey areas of Figure 1-1) achieves random fault integrity requirements of up to ASIL-B/SIL-2.