SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.26 CSI Expansion Connector

The J721E EVM supports different application specific camera expansion boards, which includes:

  • Fusion1 Serial Capture Expansion
  • Fusion2 Serial Capture Expansion

Common processor board supports to interface with these CSI expansion boards using connector of QSH-020-01-L-D-DP-A-K with 5 mm mating height allowing CSI Expansion to be stacked on bottom side of the processor board.

Camera Serial Interface CSI0 and CSI1 of J721E SoC is interfaced to this CSI expansion connector J52 on the CP board. The Common Processor board supports the Auxiliary CSI expansion connector that is reserved for CSI2 port of future J7 SoC.

Power (12 V and 3.3 V ), control GPIOs and reference clock to these CSI expansion boards are provided from Common Processor board through CSI expansion connector. Optionally auxiliary 12 V can be supplied from Common Processor board via terminal block (1757242) using external wire.

The I/O supply to these CSI expansion boards can be configured for both 3.3 V and 1.8 V using the DIP Switch SW3 Position 7.

CSI_VIO_SEL Sets I/O voltage for CSI2 Expansion Interface (LVCMOS signals)
‘0’ (OFF) = 1.8 V I/O Voltage
‘1’ (ON) = 3.3 V I/O Voltage
GUID-31BCDBCD-ED30-4EB7-9778-A181E739043C-low.gif Figure 4-45 Dual I/O Voltage Selection for CSI Expansion Interface

Table 4-33 and Table 4-34 lists the CSI expansion connector pinouts.

Table 4-33 CSI Expansion Connector J52 Pinout
CSI2 Connector Interface J52
Pin No Signal Pin No Signal
1 VCC_12V0 21 CSI0_RX3_P
2 CSI2_I2C_SCL_DV 22 CSI2_A_GPIO4_DV
3 VCC_12V0 23 CSI0_RX3_N
4 CSI2_I2C_SDA_DV 24 DGND
5 CSI0_RXCLK_P 25 CSI1_RXCLK_P
6 CSI2_A_GPIO0_DV 26 CSI1_RX3_P
7 CSI0_RXCLK_N 27 CSI1_RXCLK_N
8 CSI2_A_GPIO1_DV 28 CSI1_RX3_N
9 CSI0_RX0_P 29 CSI1_RX0_P
10 CSI2_A_REFCLK_DV 30 EXP_3V3
11 CSI0_RX0_N 31 CSI1_RX0_N
12 DGND 32 EXP_3V3
13 CSI0_RX1_P 33 CSI1_RX1_P
14 CSI2_RSTZ_DV 34 EXP_3V3
15 CSI0_RX1_N 35 CSI1_RX1_N
16 DGND 36 EXP_3V3
17 CSI0_RX2_P 37 CSI1_RX2_P
18 CSI2_A_GPIO2_DV 38 VCC_CSI_IO
19 CSI0_RX2_N 39 CSI1_RX2_N
20 CSI2_A_GPIO3_DV 40 VCC_CSI_IO
Table 4-34 CSI Expansion Connector J48 Pinout
CSI2 Connector Interface J48
Pin No Signal Pin No Signal
1 VCC_12V0 21 CSI2_RX3_P
2 CSI2_I2C_SCL_DV 22 CSI2_B_GPIO4_DV
3 VCC_12V0 23 CSI2_RX3_N
4 CSI2_I2C_SDA_DV 24 DGND
5 CSI2_RXCLK_P 25 NC
6 NC 26 NC
7 CSI2_RXCLK_N 27 NC
8 CSI2_B_GPIO1_DV 28 NC
9 CSI2_RX0_P 29 NC
10 CSI2_B_REFCLK_DV 30 EXP_3V3
11 CSI2_RX0_N 31 NC
12 DGND 32 EXP_3V3
13 CSI2_RX1_P 33 NC
14 CSI2_RSTZ_DV 34 EXP_3V3
15 CSI2_RX1_N 35 NC
16 DGND 36 EXP_3V3
17 CSI2_RX2_P 37 NC
18 CSI2_B_GPIO2_DV 38 VCC_CSI_IO
19 CSI2_RX2_N 39 NC
20 CSI2_B_GPIO3_DV 40 VCC_CSI_IO