TIDUFF4 October   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
      1. 1.1.1 General TI High Voltage Evaluation User Safety Guidelines
        1. 1.1.1.1 Safety and Precautions
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 GaN Power Stage
      2. 2.2.2 Inductor
      3. 2.2.3 Controller
      4. 2.2.4 Cooling
        1. 2.2.4.1 Heat Sink Placement
        2. 2.2.4.2 Via Placement
        3. 2.2.4.3 Copper Block
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG3100R017
      2. 2.3.2 UCD3138A
      3. 2.3.3 TPSM365R6V5
      4. 2.3.4 TMP61
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
        1. 4.1.3.1 Power Loop Optimization
        2. 4.1.3.2 Return Current Through Output Power Ground
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

4.1.3.1 Power Loop Optimization

Make sure the high-frequency current returns to the capacitor through the least inductive path possible. This reduces the peak voltage on the switch node during hard switching transitions. Place multiple capacitors close to the DRN pin of the high-side LMG3100R017 and use vias on the SRC pad of the low-side LMG3100R017 to complete the power loop through the immediate next layer (Inner Layer 1, see Figure 4-1). Additionally, add multiple higher value capacitors on the bottom layer to provide sufficient current and meet the transient ripple specifications.

TIDA-050095 Power Loop Path Figure 4-1 Power Loop Path