TIDUFG5 December   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Insulation Monitoring
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 TIDA-010985 Overview
      2. 2.2.2 Solving for the Unknown Isolation Resistances
      3. 2.2.3 Addressing Large Time Constant Cases
      4. 2.2.4 Prediction Algorithms
      5. 2.2.5 Understanding Error Sources
    3. 2.3 Highlighted Products
      1. 2.3.1 LP-MSPM0G3507
      2. 2.3.2 TPSI2240-Q1
      3. 2.3.3 RES60A-Q1
      4. 2.3.4 TLV9002-Q1
      5. 2.3.5 TPSM33620-Q1
      6. 2.3.6 TPS7A2033
      7. 2.3.7 ISOW1044
      8. 2.3.8 TSM24CA
      9. 2.3.9 TLV431B
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software
    3. 3.3 Test Setup
      1. 3.3.1 Hardware Test Setup
      2. 3.3.2 Software Test Setup
    4. 3.4 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
        1. 4.1.3.1 Layout Prints
    2. 4.2 Tools and Software [Required Topic]
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors

Test Results

Each test condition includes ten IMD measurements for statistical analysis (mean and standard deviation). Fixed-point math error is significant in some cases. Overall, the measurement errors and response time are well below the UL 2231-2 requirements (±15%, 10 seconds).

In Figure 3-6, for asymmetric faults, the error displayed is the Riso in the fault condition. The "1MΩ-1MΩ" case requires a 3s cycle to resolve due to a very large time constant.

TIDA-010985 IMD Riso Measurement Error, 1000VDC, 2s CycleFigure 3-6 IMD Riso Measurement Error, 1000VDC, 2s Cycle
TIDA-010985 IMD Ciso Error, 1MΩ to 100kΩ, 2s CycleFigure 3-7 IMD Ciso Error, 1MΩ to 100kΩ, 2s Cycle

In Figure 3-8, the relatively short time constant means that prediction for the final steady-state voltages is not necessary.

TIDA-010985 Switching Waveform Capture for 800VDC, 0.1µF, 1MΩ Symmetrical Condition Figure 3-8 Switching Waveform Capture for 800VDC, 0.1µF, 1MΩ Symmetrical Condition

In Figure 3-9, the relatively long time constant means that prediction for the final steady-state voltages is necessary.

TIDA-010985 Switching Waveform Capture for 800VDC, 1µF, 1MΩ Symmetrical ConditionFigure 3-9 Switching Waveform Capture for 800VDC, 1µF, 1MΩ Symmetrical Condition

Figure 3-10 shows the switching timing diagram. Note that each switch state stays on for about 980ms. The ADC sampling period is about 1ms. The computation time after the ADC acquisition period is about 1.98ms.

TIDA-010985 Switching Timing DiagramFigure 3-10 Switching Timing Diagram

Figure 3-11 shows a computation time of about 2ms, which includes all of the math computations such as prediction and solving for the unknowns.

TIDA-010985 Zoomed-in Timing DiagramFigure 3-11 Zoomed-in Timing Diagram