Product details

Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 10 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9.1 SFDR (dB) 70 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 10 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (Bits) 9.1 SFDR (dB) 70 Operating temperature range (C) -40 to 85 Input buffer Yes
BGA (NXA) 292 729 mm² 27 x 27
  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

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Technical documentation

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Type Title Date
* Data sheet ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC datasheet (Rev. Q) 15 Mar 2013
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 09 Dec 2013
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 May 2013
User guide Schematic and Layout Recommendations for the GSPS ADC 29 Apr 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 Apr 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 Dec 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC-LD-BB — ADC low-distortion balun board

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

In stock
Limit: 3
Evaluation board

ADC-WB-BB — ADC wideband balun board

One ADC-WB-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

In stock
Limit: 2
Evaluation board

ADC10D1500RB — The ADC10D1500 is a Low-Power, 10-Bit, Dual 1.5 GSPS or Single 3.0 GSPS AD Converter Reference Board

The ADC10D1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.5 GSPS (Non-DES Mode) or for a single channel up to 3.0 GSPS (DES Mode (...)

In stock
Limit: 3
Application software & framework

WAVEVISION5 — Data acquisition and analysis software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Simulation model

ADC10D1000 IBIS Model

SNAM011.ZIP (83 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00113 — Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic performance (...)
Package Pins Download
BGA (NXA) 292 View options

Ordering & quality

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