Product details

Sample rate (Max) (MSPS) 130 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Input range (Vp-p) 2.4 Power consumption (Typ) (mW) 755 Architecture Pipeline SNR (dB) 78.5 ENOB (Bits) 12.7 SFDR (dB) 95.5 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 130 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Input range (Vp-p) 2.4 Power consumption (Typ) (mW) 755 Architecture Pipeline SNR (dB) 78.5 ENOB (Bits) 12.7 SFDR (dB) 95.5 Operating temperature range (C) -40 to 85 Input buffer No
WQFN (NKD) 64 81 mm² 9 x 9
  • Dual Supplies: 1.8V and 3.0V Operation
  • On Chip Automatic Calibration During Power-Up
  • Low Power Consumption
  • Multi-Level Multi-Function Pins for CLK/DF and PD
  • Power-Down and Sleep Modes
  • On Chip Precision Reference and Sample-and-Hold Circuit
  • On Chip Low Jitter Duty-Cycle Stabilizer
  • Offset Binary or 2's Complement Data Format
  • Full Data Rate LVDS Output Port
  • 64-pin WQFN Package (9x9x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • High IF Sampling Receivers
  • Multi-carrier Base Station Receivers
    • GSM/EDGE, CDMA2000, UMTS, LTE, and WiMax
  • Test and Measurement Equipment
  • Communications Instrumentation
  • Data Acquisition
  • Portable Instrumentation

All trademarks are the property of their respective owners.

  • Dual Supplies: 1.8V and 3.0V Operation
  • On Chip Automatic Calibration During Power-Up
  • Low Power Consumption
  • Multi-Level Multi-Function Pins for CLK/DF and PD
  • Power-Down and Sleep Modes
  • On Chip Precision Reference and Sample-and-Hold Circuit
  • On Chip Low Jitter Duty-Cycle Stabilizer
  • Offset Binary or 2's Complement Data Format
  • Full Data Rate LVDS Output Port
  • 64-pin WQFN Package (9x9x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • High IF Sampling Receivers
  • Multi-carrier Base Station Receivers
    • GSM/EDGE, CDMA2000, UMTS, LTE, and WiMax
  • Test and Measurement Equipment
  • Communications Instrumentation
  • Data Acquisition
  • Portable Instrumentation

All trademarks are the property of their respective owners.

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.

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Type Title Date
* Data sheet ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs datasheet (Rev. E) 15 Mar 2013
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
User guide ADC16V130 16-Bit, 130 MSPS AD Converter with LVDS Outputs Eval Bd User Guide (Rev. A) 26 Jul 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 Apr 2013
Application note Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 26 Apr 2013
Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) 22 Apr 2013
User guide SP16130CH4RB Low IF Receiver Reference Design User Guide 27 Jan 2012

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