ADC12D1600QML-SP

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Product details

Sample rate (Max) (MSPS) 1600, 3200 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
Sample rate (Max) (MSPS) 1600, 3200 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2400 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 58.2 ENOB (Bits) 9.3 SFDR (dB) 67.3 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
CCGA (NAA) 376
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package
  • Total Ionizing Dose (TID) to 300 krad(Si)
  • Single Event Latch-up (SEL) > 120 MeV-cm2/mg
  • Wide Temperature Range –55°C to +125°C
  • Low Power Consumption
  • R/W SPI for Extended Control Mode or Simple Pin Control Mode
  • Interleaved Timing Automatic with Manual Skew Adjust
  • Auto-Sync Function for Multi-Chip Systems
  • Time Stamp Feature to Capture External Trigger
  • Test Patterns at Output for System Debug
  • 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs
  • Single 1.9V Power Supply
  • 376 CPGA Hermetic Package

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.

The ADC12D1600QML is a low power, high performance CMOS analog-to-digital converter that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a Low Sampling Power Saving Mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS.

The ADC1600QML provides a flexible parallel LVDS interface which has multiple SPI programmable options to facilitate board design and ASIC/FPGA data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common mode voltage. The output of each channel is configurable in either 1:1 non-demuxed or 1:2 demuxed modes. If used as a single channel ADC, there is an option for 1:4 demuxing of the output. The product comes in a hermetic 376 CPGA package for harsh environments.

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Technical documentation

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Type Title Date
* Data sheet ADC12D1600QML 12-Bit, 3.2/2.0 GSPS RF Sampling ADC datasheet 17 Dec 2012
* Radiation & reliability report ADC12D1600QML-SP/ADC12D1620QML-SP Single-Event Effects (SEE) Radiation Report 27 Jul 2020
* Radiation & reliability report ADC12D1600CCMLS TID Report 17 Jan 2013
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 04 May 2012
Selection guide TI Space Products (Rev. I) 03 Mar 2022
Application note Understanding Op Amp Noise in Audio Circuits PDF | HTML 14 Jun 2021
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations 18 May 2020
Application note Single-Event Effects Confidence Interval Calculations 14 Jan 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 17 Jun 2019
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 Feb 2017
Application note Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 07 Dec 2015
Application note Signal Chain Noise Figure Analysis 29 Oct 2014
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 06 Aug 2014
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 May 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 Dec 2012
More literature ADC12Dxx00RF Direct RF-Sampling ADC Family 16 May 2012

Design & development

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Simulation model

ADC12D1600 IBIS Model (Rev. A) ADC12D1600 IBIS Model (Rev. A)

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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CCGA (NAA) 376 View options

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