CD74AC74 Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset | TI.com

CD74AC74
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Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset - CD74AC74
Datasheet
 

Description

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Features

  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
CD74AC74 Order now AC     CMOS     CMOS     1.5     5.5     24     -24     Catalog     PDIP | 14
SOIC | 14    
CD54AC74 Samples not available AC     CMOS     CMOS     1.5     5.5     24     -24     Military     CDIP | 14