SN74AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset | TI.com

SN74AHC74
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset - SN74AHC74
Datasheet
 

Description

The ’AHC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Features

  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74AHC74 Order now AHC     CMOS     CMOS     2     5.5     50     -50     Catalog     PDIP | 14
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
TVSOP | 14
VQFN | 14    
SN54AHC74 Samples not available AHC     CMOS     CMOS     2     5.5     50     -50     Military     CDIP | 14
CFP | 14
LCCC | 20