Packaging information
| Package | Pins TSSOP (PW) | 24 |
| Operating temperature range (°C) 0 to 85 |
| Package qty | Carrier 60 | TUBE |
Features for the CDCVF2509
- Designed to meet and exceed PC133 SDRAM registered DIMM specification Rev. 1.1
- Spread Spectrum Clock-compatible
- Operating frequency: 50MHz to 175MHz
- Static phase error distribution at 66MHz to 166MHz is ±125ps
- Jitter (cyc - cyc) at 66MHz to 166MHz is typical = 70ps
- Advanced deep submicron process results in more than 40% lower power consumption versus current generation PC133 devices
- Available in plastic 24-pin TSSOP
- Phase-lock loop clock distribution for synchronous DRAM applications
- Distributes one clock input to one bank of five and one bank of four outputs
- Separate output enable for each output bank
- External feedback (FBIN) terminal is used to synchronize the outputs to the clock input
- 25-Ω On-chip series damping resistors
- No external RC network required
- Operates at 3.3V
Description for the CDCVF2509
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The device uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The device is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3V VCCand provides integrated series-damping resistors designed for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately through the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK. When the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
The device is based on PLL circuitry, therefore the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground.
The CDCVF2509A is characterized for operation from 0°C to 85°C.
For application information, see the High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) application notes.