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CDCVF2509

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3.3-V phase-lock loop clock driver with 9 outputs for DRAM applications

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Data sheet

CDCVF2509

ACTIVE
Data sheet Order now

Product details

Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 175 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 100 Features SDR Operating temperature range (°C) 0 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 175 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 100 Features SDR Operating temperature range (°C) 0 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2509A (SCAS765) as a Replacement for This Device
  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
  • Spread Spectrum Clock Compatible
  • Operating Frequency 50 MHz to 175 MHz
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
  • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for
    Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of
    Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output
    Bank
  • External Feedback (FBIN) Terminal Is Used
    to Synchronize the Outputs to the Clock
    Input
  • 25- On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • APPLICATIONS
    • DRAM Applications
    • PLL Based Clock Distributors
    • Non-PLL Clock Buffer
  • Use CDCVF2509A (SCAS765) as a Replacement for This Device
  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
  • Spread Spectrum Clock Compatible
  • Operating Frequency 50 MHz to 175 MHz
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
  • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for
    Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of
    Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output
    Bank
  • External Feedback (FBIN) Terminal Is Used
    to Synchronize the Outputs to the Clock
    Input
  • 25- On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • APPLICATIONS
    • DRAM Applications
    • PLL Based Clock Distributors
    • Non-PLL Clock Buffer

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground.

The CDCVF2509A is characterized for operation from 0°C to 85°C.

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground.

The CDCVF2509A is characterized for operation from 0°C to 85°C.
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* Data sheet CDCVF2509: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. D) 05 Feb 2010
Application note Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLs 23 Jul 2004

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