ISO5852S

SOIC (DW)

16

77 mm² 10.3 x 7.5

100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at V_CM = 1500 V
Split Outputs to Provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients Shorter Than 20 ns
Operating Temperature: –40°C to +125°C Ambient
Isolation Surge Withstand Voltage 12800-V_PK
Safety-Related Certifications:
- 8000-V_PK V_IOTM and 2121-V_PK V_IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
- 5700-V_RMS Isolation for 1 Minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
- TUV Certification per EN 61010-1 and EN 60950-1
- GB4943.1-2011 CQC Certification

All trademarks are the property of their respective owners.

100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at V_CM = 1500 V
Split Outputs to Provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients Shorter Than 20 ns
Operating Temperature: –40°C to +125°C Ambient
Isolation Surge Withstand Voltage 12800-V_PK
Safety-Related Certifications:
- 8000-V_PK V_IOTM and 2121-V_PK V_IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
- 5700-V_RMS Isolation for 1 Minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
- TUV Certification per EN 61010-1 and EN 60950-1
- GB4943.1-2011 CQC Certification

All trademarks are the property of their respective owners.

The ISO5852S device is a 5.7-kV_RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V_EE2, the gate-driver output is pulled hard to the V_EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V_EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

For all available packages, see the orderable addendum at the end of the data sheet.

The ISO5852S device is a 5.7-kV_RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V_EE2, the gate-driver output is pulled hard to the V_EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V_EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

For all available packages, see the orderable addendum at the end of the data sheet.

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Technical documentation

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	Type	Title	Date
*	Data sheet	ISO5852S High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet (Rev. B)	16 Jan 2017
	Certificate	TUV Certificate for Isolation Devices (Rev. J)	23 Aug 2021
	Certificate	CQC Certification (Rev. G)	19 Aug 2021
	Application note	Digital Isolator Design Guide (Rev. C)	12 Jul 2021
	Certificate	CSA Certification (Rev. Q)	14 Jun 2021
	Certificate	VDE certificate for reinforced isolation for DIN VDE V 0884-11:2017-01 (Rev. O)	14 Jun 2021
	Certificate	UL Certification (Rev. O)	03 Feb 2021
	Application note	External Gate Resistor Selection Guide (Rev. A)	28 Feb 2020
	Application note	Understanding Peak IOH and IOL Currents (Rev. A)	28 Feb 2020
	Application note	Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting	26 Feb 2020
	White paper	Isolation in AC Motor Drives: Understanding the IEC 61800-5-1 Safety Standard (Rev. A)	19 Sep 2019
	Technical article	Designing highly efficient, powerful and fast EV charging stations	06 Aug 2019
	Technical article	How to achieve higher system robustness in DC drives, part 3: minimum input pulse	19 Sep 2018
	Application note	Pushing the envelope with high-performance digital-isolation technology (Rev. A)	22 Aug 2018
	Technical article	How to achieve higher system robustness in DC drives, part 2: interlock and deadtime	30 May 2018
	Technical article	Boosting efficiency for your solar inverter designs	24 May 2018
	User guide	ISO5852SDW Driving and Protecting SiC and IGBT Power Modules	24 May 2018
	White paper	Isolation in solar power converters: Understanding the IEC62109-1 safety standar (Rev. A)	18 May 2018
	Application note	Isolation Glossary (Rev. A)	19 Sep 2017
	Application note	4Q 2015 Analog Applications Journal	30 Oct 2015
	Application note	Common-mode transient immunity for isolated gate drivers	30 Oct 2015
	Application note	Pushing the envelope with high-performance digital-isolation technology	30 Oct 2015
	User guide	ISO5852S Evaluation Module User's Guide (Rev. A)	08 Sep 2015
	White paper	Understanding electromagnetic compliance tests in digital isolators	17 Oct 2014
	White paper	High-voltage reinforced isolation: Definitions and test methodologies	16 Oct 2014
	Application note	Shelf-Life Evaluation of Lead-Free Component Finishes	24 May 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ISO5852SDWEVM-017 — Driving and Protection Evaluation Board for SiC and IGBT Power Modules

The ISO5852SDWEVM-017 is a compact, dual chanel isolated gate driver board providing drive, bias voltages, protection and diagnostic needed for half-bridge Sic MOSFET and IGBT Power Modules in standard 62-mm package. This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in (...)

User guide

In stock

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Evaluation board

ISO5852SEVM — Reinforced Isolated IGBT Gate Driver Evaluation Module

This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.

User guide

In stock

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Simulation model

ISO5852S IBIS Model

SLLM283.ZIP (33 KB) - IBIS Model

Simulation model

ISO5852S PSpice Transient Model (Rev. A)

SLLM300A.ZIP (232 KB) - PSpice Model

Simulation model

ISO5852S TINA-TI SPICE Model

SLLM435.ZIP (31 KB) - TINA-TI Spice Model

Simulation model

ISO5852S TINA-TI Reference Design

SLLM436.TSC (1537 KB) - TINA-TI Reference Design

Simulation model

ISO5852S Unencrypted PSPICE Transient Model

SLLM446.ZIP (4 KB) - PSpice Model

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Design tool

ISO5852SDWEVM-017 Design Files

SLLR117.ZIP (7300 KB)

Reference designs

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TIDA-00195 — Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System Reference Design

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