Product details

Frequency (max) (MHz) 5500 Frequency (min) (MHz) 20 Normalized PLL phase noise (dBc/Hz) -231 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -126 Features Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 250 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 5500 Frequency (min) (MHz) 20 Normalized PLL phase noise (dBc/Hz) -231 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -126 Features Integer-boundary spurs (IBS) removal, Integrated VCO, Phase adjustment, Wideband Current consumption (mA) 250 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFN (RHA) 40 36 mm² 6 x 6
  • Output Frequency Range from 20 to 5500 MHz
  • Industry Leading Phase Noise Performance
    • VCO Phase Noise: –144.5 dBc/Hz at 1-MHz Offset for 1.8-GHz Output
    • Normalized PLL Noise Floor: –231 dBc/Hz
    • Normalized PLL Flicker Noise: –126 dBc/Hz
    • 47-fs RMS Jitter (12 kHz to 20 MHz) for 1.8 GHz Output
  • Input Clock Frequency Up to 1400 MHz
  • Phase Detector Frequency Up to 200 MHz, and Up to 400 MHz in Integer-N Mode
  • Supports Fractional-N and Integer-N Modes
  • Dual Differential Outputs
  • Innovative Solution to Reduce Spurs
  • Programmable Phase Adjustment
  • Programmable Charge Pump Current
  • Programmable Output Power Level
  • SPI or uWire (4-Wire Serial Interface)
  • Single Power Supply Operation: 3.3 V
  • Output Frequency Range from 20 to 5500 MHz
  • Industry Leading Phase Noise Performance
    • VCO Phase Noise: –144.5 dBc/Hz at 1-MHz Offset for 1.8-GHz Output
    • Normalized PLL Noise Floor: –231 dBc/Hz
    • Normalized PLL Flicker Noise: –126 dBc/Hz
    • 47-fs RMS Jitter (12 kHz to 20 MHz) for 1.8 GHz Output
  • Input Clock Frequency Up to 1400 MHz
  • Phase Detector Frequency Up to 200 MHz, and Up to 400 MHz in Integer-N Mode
  • Supports Fractional-N and Integer-N Modes
  • Dual Differential Outputs
  • Innovative Solution to Reduce Spurs
  • Programmable Phase Adjustment
  • Programmable Charge Pump Current
  • Programmable Output Power Level
  • SPI or uWire (4-Wire Serial Interface)
  • Single Power Supply Operation: 3.3 V

The LMX25 82 device is a low-noise, wideband RF PLL with integrated VCO that supports a frequency range from 20 MHz to 5.5 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. Integrated noise of 47 fs for 1.8-GHz output makes it an ideal low-noise source. Combining best-in-class PLL and integrated VCO noise with integrated LDOs, this device removes the need for multiple discrete devices in high performance systems.

The device accepts input frequencies up to 1.4 GHz, which combined with frequency dividers and programmable low noise multiplier allows flexible frequency planning. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In Fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports a fast calibration option which takes less than 25 µs.

This performance is achieved by using single 3.3-V supply. It supports 2 flexible differential outputs that can be configured as single-ended outputs as well. Users can choose to program one output from the VCO and the second from the channel divider. When not being used, each output can be muted separately.

The LMX25 82 device is a low-noise, wideband RF PLL with integrated VCO that supports a frequency range from 20 MHz to 5.5 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. Integrated noise of 47 fs for 1.8-GHz output makes it an ideal low-noise source. Combining best-in-class PLL and integrated VCO noise with integrated LDOs, this device removes the need for multiple discrete devices in high performance systems.

The device accepts input frequencies up to 1.4 GHz, which combined with frequency dividers and programmable low noise multiplier allows flexible frequency planning. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In Fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports a fast calibration option which takes less than 25 µs.

This performance is achieved by using single 3.3-V supply. It supports 2 flexible differential outputs that can be configured as single-ended outputs as well. Users can choose to program one output from the VCO and the second from the channel divider. When not being used, each output can be muted separately.

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Technical documentation

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* Data sheet LMX2582 High Performance, Wideband PLLatinum™ RF Synthesizer With Integrated VCO datasheet (Rev. E) PDF | HTML 03 Aug 2022
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Oct 2024
Application note Clocking Optimization for RF Sampling Analog-to-Digital Converters (Rev. A) PDF | HTML 07 Apr 2021
Technical article Don’t let bad reference signals destroy the phase noise in your PLL/synthesizer PDF | HTML 10 Jan 2017
Technical article What’s the fuss about noise in RF sampling converters? PDF | HTML 20 Jul 2016
Technical article Push your receiver bandwidths past 1-GHz in high-end applications PDF | HTML 26 May 2016
Technical article How to estimate the phase noise of a PLL with basic datasheet specifications PDF | HTML 02 Mar 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC08DJ3200EVM — ADC08DJ3200 8-Bit, Dual 3.2GSPS or Single 6.4GSPS, RF-Sampling ADC evaluation Module

The ADC08DJ3200 evaluation module (EVM) is designed to evaluate the ADC08DJ3200 high-speed analog-to-digital converter (ADCs). The EVM is populated with the ADC08DJ3200, an 8-bit, dual-channel 3.2GSPS or single-channel 6.4GSPS ADC with JESD204B interface.
User guide: PDF
Not available on TI.com
Evaluation board

ADC12DJ2700EVM — ADC12DJ2700 12-bit, dual 2.7GSPS or single 5.4GSPS, RF-sampling ADC evaluation module

The ADC12DJ2700 evaluation module (EVM) is designed to evaluate the ADC12DJ2700 high-speed analog-to-digital converter (ADCs). The EVM is populated with the ADC12DJ2700, a 12-bit, dual-channel 2.7GSPS or single-channel 5.4GSPS ADC with JESD204B interface.
User guide: PDF
Not available on TI.com
Evaluation board

ADC12DJ3200EVM — ADC12DJ3200 12-bit, dual 3.2GSPS or single 6.4GSPS, RF-sampling ADC evaluation module

The ADC12DJ3200 evaluation module (EVM) is designed to evaluate the ADC12DJ3200 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ3200, a 12-bit, dual-channel 3.2GSPS or single-channel 6.4GSPS ADC with JESD204B interface and allows for evaluation of all (...)
User guide: PDF
Not available on TI.com
Evaluation board

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP evaluation module

The ADC12DJ3200 evaluation module (EVM) is designed to evaluate the ADC12DJ3200QML-SP high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ3200QML-SP, a space-grade 12-bit, dual-channel 4GSPS or single-channel 8GSPS ADC with JESD204B interface.
User guide: PDF
Not available on TI.com
Evaluation board

ADC12DJ5200RFEVM — ADC12DJ5200RF RF-sampling 12-bit dual 5.2GSPS or single 10.4GSPS ADC evaluation module

The ADC12DJ5200RF evaluation module (EVM) is designed to evaluate the ADC12DJ5200RF family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ5200RF, a 12-bit, dual-channel 5.2GSPS or single-channel 10.4GSPS ADC with JESD204B interface and allows for evaluation (...)
User guide: PDF | HTML
Evaluation board

ADC12DL2500EVM — ADC12DL2500 evaluation module

The ADC12DL2500 evaluation module (EVM) is designed to evaluate the ADC12DL2500 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DL2500, a 12-bit, dual-channel 2.5GSPS or single-channel 5GSPS ADC with LVDS interface and allows for evaluation of all (...)
User guide: PDF | HTML
Not available on TI.com
Evaluation board

ADC12DL3200EVM — ADC12DL3200 12-bit, dual 3.2GSPS or single 6.4GSPS, RF-sampling ADC evaluation module

The ADC12DJ3200 evaluation module (EVM) is designed to evaluate the ADC12DJ3200 high-speed analog-to-digital converter (ADCs). The EVM is populated with the ADC12DJ3200, a 12-bit, dual-channel 3.2GSPS or single-channel 6.4GSPS ADC with LVDS interface.
User guide: PDF | HTML
Not available on TI.com
Evaluation board

LMX2582EVM — LMX2582EVM High Performance, Wideband Frequency PLLatinum RF Synthesizer With Integrated VCO

This Evaluation Module is for the LMX2582, which outputs very high frequency signals with industry leading phase noise. The integrated VCO allows minimal discrete external components to design. The PCB is optimized for performance as well as designed for easy customization of the loop filter. An (...)

User guide: PDF
Not available on TI.com
Evaluation board

TSW40RF80EVM — 2T2R RF-Sampling Transceiver w/ Dual 14-Bit 3GSPS ADC/9GSPS DAC Clocking Solution Evaluation Module

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The (...)

User guide: PDF
Not available on TI.com
Support software

TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware

Supported products & hardware

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Simulation model

LMX2582 IBIS Model (Rev. A)

SNAM199A.ZIP (44 KB) - IBIS Model
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design tool

PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Download options
Reference designs

TIDA-01161 — 1-GHz Signal Bandwidth RF Sampling Receiver Reference Design

The RF sampling architecture offers an alternative to the traditional super-heterodyne architecture. An RF sampling analog-to-digital converter (ADC) operates at a high sampling rate and converts signals directly from radio frequencies (RF) to digital. Because of the high sampling rate, the RF (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01435 — High-Bandwidth Zero-IF Reference Design for Microwave Backhaul

The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01442 — Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design

This reference design uses the ADC12DJ3200 evaluation module (EVM) to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C- and part of X-band. The wide analog-input bandwidth and high-sampling rate (6.4 GSPS) of the analog-to-digital converter (ADC) provides (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01247 — Efficient, LDO-Less, Power-Supply Network Reference Design for RF-Sampling ADC

This reference design demonstrates a simplified and efficient network to power an ADC32RFxx. All three power domains of the analog-to-digital converter (ADC) are supplied using a switching regulator to enable the use of a power-supply network without a low-dropout (LDO) linear regulator. (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01163 — Multi-band RF Sampling Receiver Reference Design

The RF sampling receiver captures signals directly in the radio frequency (RF) band. In a multi-band application the desired signals are not very wide band but they are spaced far apart within the spectrum. The reference design captures signals in different RF bands and digitally down-converts them (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01016 — Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers

TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel, 14-bit, 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz, and it captures signals up to 4 (...)
Design guide: PDF
Schematic: PDF
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VQFN (RHA) 40 Ultra Librarian

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