TIDA-01016

Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers

TIDA-01016

Design files

Overview

TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel, 14-bit, 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz, and it captures signals up to 4 GHz. This design showcases the clocking solution using the LMX2582, to achieve the best SNR performance of ADC32RF45 at higher input frequencies used in microwave backhaul applications.

Features
  • 3 GHz low-phase noise clocking solution for RF sampling ADC with >51 dB SNR @ 3.65 GHz input
  • 4GHz high frequency input signal capture capability
  • Large signal bandwidth, high dynamic range RF sampling receiver solution

A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUCC8A.PDF (671 K)

Reference design overview and verified performance test data

TIDRNS2.PDF (141 K)

Detailed schematic diagram for design layout and components

TIDRNS3.PDF (66 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRNS6.ZIP (1568 K)

Files used for 3D models or 2D drawings of IC components

TIDCCO8.ZIP (685 K)

Design file that contains information on physical board layer of design PCB

TIDRNS5.PDF (1991 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

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Clock jitter cleaners & synchronizers

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High-speed ADCs (>10MSPS)

ADC32RF45Dual-channel, 14-bit, 3-GSPS, RF-sampling analog-to-digital converter (ADC)

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Linear & low-dropout (LDO) regulators

TPS742011.5-A, low-VIN (0.8-V), low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator

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Linear & low-dropout (LDO) regulators

TPS7A471-A, 36-V, low-noise, high-PSRR, low-dropout voltage regulator with enable

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Linear & low-dropout (LDO) regulators

TPS7A72002-A, low-VIN (1.43-V), ultra-low-dropout voltage regulator with power good & enable

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RF PLLs & synthesizers

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eFuses & hot swap controllers

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Technical documentation

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Type Title Date
* Design guide Clocking Ref Design for RF Sampling ADCs in Signal Analyzers and Wireless Tester (Rev. A) Dec. 05, 2016

Related design resources

Hardware development

EVALUATION BOARD
ADC32RF45EVM ADC32RF45 evaluation module for dual-channel, 14-bit, 3-GSPS, RF-sampling ADC TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

Reference designs

REFERENCE DESIGN
TIDA-01015 4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers TIDA-01017 High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01022 Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers TIDA-01161 1-GHz Signal Bandwidth RF Sampling Receiver Reference Design

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