Product details

Operating temperature range (C) -40 to 85
Operating temperature range (C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Dual-Channel, 10-Gbps, Multi-Rate Transceiver
  • Supports All CPRI and OBSAI Data Rates From 1 Gbps to 10 Gbps
  • Integrated Latency Measurement Function, Accuracy up to 814 ps
  • Supports SERDES Operation With up to 10-Gbps Data Rate on the High-Speed Side and up to 5G bps on the Low-Speed Side
  • Differential CML I/Os on Both High-Speed and Low-Speed Sides
  • Shared or Independent Reference Clock Per Channel
  • Loopback Capability on Both High-Speed and Low-Speed Sides, OBSAI Compliant
  • Supports Data Retime Operation
  • Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency, Low-Frequency, Mixed-Frequency, and CRPAT Long and Short Pattern Generation and Verification
  • Two Power Supplies: 1-V Core, and 1.5-V or 1.8-V I/O
  • Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane or Cable Reach on Both High-Speed and Low-Speed Sides
  • Programmable Transmit Output Swing on Both High-Speed and Low-Speed Sides.
  • Minimum Receiver Differential Input Threshold of 100 mVpp
  • Loss-of-Signal (LOS) Detection
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65-nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Power Consumption: 1.6 W Typical
  • Device Package: 13-mm × 13-mm, 144-pin PBGA, 1-mm Ball-Pitch
  • Dual-Channel, 10-Gbps, Multi-Rate Transceiver
  • Supports All CPRI and OBSAI Data Rates From 1 Gbps to 10 Gbps
  • Integrated Latency Measurement Function, Accuracy up to 814 ps
  • Supports SERDES Operation With up to 10-Gbps Data Rate on the High-Speed Side and up to 5G bps on the Low-Speed Side
  • Differential CML I/Os on Both High-Speed and Low-Speed Sides
  • Shared or Independent Reference Clock Per Channel
  • Loopback Capability on Both High-Speed and Low-Speed Sides, OBSAI Compliant
  • Supports Data Retime Operation
  • Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency, Low-Frequency, Mixed-Frequency, and CRPAT Long and Short Pattern Generation and Verification
  • Two Power Supplies: 1-V Core, and 1.5-V or 1.8-V I/O
  • Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane or Cable Reach on Both High-Speed and Low-Speed Sides
  • Programmable Transmit Output Swing on Both High-Speed and Low-Speed Sides.
  • Minimum Receiver Differential Input Threshold of 100 mVpp
  • Loss-of-Signal (LOS) Detection
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65-nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Power Consumption: 1.6 W Typical
  • Device Package: 13-mm × 13-mm, 144-pin PBGA, 1-mm Ball-Pitch

The TLK10002 device is a dual-channel, multi-rate transceiver intended for use in high-speed bidirectional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high-speed applications. It supports all the CPRI and OBSAI rates from 1.2288 Gbps to 9.8304 Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low-speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high-speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high-speed side data inputs. The deserialized 8B/10B encoded data is presented on the low-speed side outputs. Depending on the serialization or deserialization ratio, the low-speed side data rate can range from 0.5 Gbps to 5 Gbps and the high-speed side data rate can range from 1 Gbps to 10 Gbps. Both low-speed and high-speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.

The TLK10002 performs data serialization or deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high-speed side.

The TLK10002 provides two low-speed side and two high-speed side loopback modes for self-test and system diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High, Low, Mixed, and CRPAT long and short pattern generation and verification.

The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low-speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization or deserialization ratios.

The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.

The TLK10002 device is a dual-channel, multi-rate transceiver intended for use in high-speed bidirectional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high-speed applications. It supports all the CPRI and OBSAI rates from 1.2288 Gbps to 9.8304 Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low-speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high-speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high-speed side data inputs. The deserialized 8B/10B encoded data is presented on the low-speed side outputs. Depending on the serialization or deserialization ratio, the low-speed side data rate can range from 0.5 Gbps to 5 Gbps and the high-speed side data rate can range from 1 Gbps to 10 Gbps. Both low-speed and high-speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.

The TLK10002 performs data serialization or deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high-speed side.

The TLK10002 provides two low-speed side and two high-speed side loopback modes for self-test and system diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High, Low, Mixed, and CRPAT long and short pattern generation and verification.

The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low-speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization or deserialization ratios.

The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.

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Technical documentation

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Type Title Date
* Data sheet TLK10002 10-Gbps, Dual-Channel, Multi-Rate Transceiver datasheet (Rev. B) 28 Jul 2016
Technical article Challenges in high-speed communications 13 Jun 2014
Application note Driving the TLK10002 10Gpbs SERDES with the CDCM6208 Clock Generator 14 Dec 2012
Application note TLK10002 Latency Measurement in Wireless Base Station System 13 Mar 2012
User guide TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver EVM 09 May 2011
User guide TLK10002 Dual-Chnl, 10-Gbps, Multi-Rate Transceiver EVM Graphical User Interface 07 May 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TLK10002EVM — TLK10002EVM Evaluation Module

Motherboard evaluation module for TLK10002.
In stock
Limit: 1
Evaluation board

TLK10002FPGAEVM — TLK10002FPGAEVM evaluation module

FPGA daughterboard for the TLK10002 device. The TLK10002 device is a dual-channel, multi-rate transceiver.
In stock
Limit: 1
Evaluation board

TLK10002SMAEVM — TLK10002SMAEVM Evaluation Module

SMA breakout daughterboard for TLK10002.
In stock
Limit: 1
GUI for evaluation module (EVM)

TLK10002 EVM GUI

SLLC422.ZIP (8050 KB)
Simulation model

TLK10002 HSPICE Model

SLLM143.ZIP (9023 KB) - HSpice Model
Simulation model

TLK10002 IBIS Model

SLLM144.ZIP (61 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Schematic

TI Lane Align Ref Design v04

SLLC431.ZIP (4947 KB)
Package Pins Download
FCBGA (CTR) 144 View options

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