Low power C55x fixed point DSP- up to 100MHz, USB, LCD interface, FFT HWA, SAR ADC

TMS320VC5505

ACTIVE

Product details

DSP 1 C55x DSP MHz (Max) 100, 60 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog
DSP 1 C55x DSP MHz (Max) 100, 60 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 10-ns Instruction Cycle Time
    • 60-, 100-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 200 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Fully Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
    • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, or I2C EEPROM
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
  • (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • Applications:
    • Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
    • Echo Cancellation Headphones
    • Portable Medical Devices
    • Voice Applications
    • Industrial Controls
    • Fingerprint Biometrics
    • Software Defined Radio

All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 10-ns Instruction Cycle Time
    • 60-, 100-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 200 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Fully Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
    • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, or I2C EEPROM
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
  • (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • Applications:
    • Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
    • Echo Cancellation Headphones
    • Portable Medical Devices
    • Voice Applications
    • Industrial Controls
    • Fingerprint Biometrics
    • Software Defined Radio

All trademarks are the property of their respective owners.

The TMS320VC5505 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The VC5505 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM. Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). The DMA controller provides data movement for sixteen independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. This device also includesthree general-purpose timers with one configurable as a watchdog timer, and a analog phase-locked loop (APLL) clock generator.

In addition, the VC5505 includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The VC5505 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The VC5505 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support

The TMS320VC5505 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The VC5505 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM. Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). The DMA controller provides data movement for sixteen independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. This device also includesthree general-purpose timers with one configurable as a watchdog timer, and a analog phase-locked loop (APLL) clock generator.

In addition, the VC5505 includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The VC5505 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The VC5505 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support

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Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

Technical documentation

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Type Title Date
* Data sheet TMS320VC5505 Fixed-Point Digital Signal Processor datasheet (Rev. B) 12 Feb 2010
* Errata TMS320VC5505/VC5504 Fixed-Point DSP Silicon Errata (Silicon Revision 1.4) (Rev. C) 15 Jan 2013
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
User guide TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 30 Sep 2015
Application note FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 09 Jan 2013
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 Aug 2012
User guide TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 13 Jan 2012
User guide TMS320VC5505 DSP System User's Guide (Rev. C) 12 Jan 2012
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 15 Dec 2011
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. I) 09 Nov 2011
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 09 Nov 2011
Application note Using the TMS320VC5505/04 Bootloader (Rev. A) 10 May 2010
User guide TMS320VC5505/04 DSP External Memory Interface (EMIF) User's Guide (Rev. A) 17 Mar 2010
User guide TMS320VC5505/5504 DSP Inter-IC Sound User's Guide (Rev. A) 25 Jan 2010
User guide TMS320C5515/05/VC05 DSP Liquid Crystal Display Controller User's Guide 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output User's Guide 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Inter-Integrated Circuit (I2C) Peripheral UG (Rev. A) 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Serial Peripheral Interface (SPI) UG 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide 21 Sep 2009
User guide TMS320C5515/14/05/04/VC05/VC04 DSP UART User's Guide 21 Sep 2009
User guide TMS320VC5505/5504 DSP Direct Memory Access (DMA) Controller User's Guide 21 Sep 2009
User guide TMS320VC5505/5504 DSP Real-Time Clock User's Guide 21 Sep 2009
User guide TMS320VC5505/5504 DSP Universal Serial Bus 2.0 (USB) User's Guide 21 Sep 2009
More literature C5505 eZDSP UBS Stick Dev Tool Product Bulletin 08 Sep 2009
More literature C5504 and C5505 DSP Frequently Asked Questions (Rev. A) 07 Aug 2009
More literature TMS320VC5504 and TMS320VC5505 DSPs Product Bulletin (Rev. C) 06 Aug 2009
More literature Solutions for Personal Medical Application Development 26 Jun 2009
User guide TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 24 Jun 2009
User guide TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 24 Jun 2009
User guide TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 17 Jun 2009
User guide TMS320C55x Assembly Language Tools User's Guide (Rev. H) 31 Jul 2004
User guide TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. F) 31 Dec 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Driver or library

SPRC100 — TMS320C55x DSP Library (DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Software codec

C55XCODECS — CODECS - Optimized for C55x Devices

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
Simulation model

VC5505 ZCH IBIS Model (Rev. B)

SPRM390B.ZIP (445 KB) - IBIS Model
Simulation model

VC5505 ZCH BSDL Model (Rev. B)

SPRM391B.ZIP (5 KB) - BSDL Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Package Pins Download
NFBGA (ZCH) 196 View options

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