TMS320VC5510A

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Product details

DSP 1 C55x DSP MHz (Max) 160, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85, 0 to 85
DSP 1 C55x DSP MHz (Max) 160, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85, 0 to 85
NFBGA (GBC) 240 225 mm² 15 x 15 NFBGA (ZAV) 240 225 mm² 15 x 15
  • High-Performance, Low-Power, Fixed-Point TMS320C55x™; Digital Signal Processor (DSP)
    • 6.25-/5-ns Instruction Cycle Time
    • 160-/200-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS))
    • Two Arithmetic/Logic Units
    • One Internal Program Bus
    • Three Internal Data/Operand Read Buses
    • Two Internal Data/Operand Write Buses
  • Instruction Cache (24K Bytes)
  • 160K x 16-Bit On-Chip RAM Composed of:
    • Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
    • 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM)(256K Bytes)
  • 16K × 16-Bit On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Memory Interface (EMIF) With Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst SRAM (SBSRAM)
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI)
    • Programmable Digital Phase-Locked Loop (DPLL) Clock Generator
    • Eight General-Purpose I/O (GPIO) Pins and Dedicated General-Purpose Output (XF)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (GGW Suffix)
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (ZGW Suffix) [Lead-Free]
  • 3.3-V I/O Supply Voltage
  • 1.6-V Core Supply Voltage

TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.

  • High-Performance, Low-Power, Fixed-Point TMS320C55x™; Digital Signal Processor (DSP)
    • 6.25-/5-ns Instruction Cycle Time
    • 160-/200-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS))
    • Two Arithmetic/Logic Units
    • One Internal Program Bus
    • Three Internal Data/Operand Read Buses
    • Two Internal Data/Operand Write Buses
  • Instruction Cache (24K Bytes)
  • 160K x 16-Bit On-Chip RAM Composed of:
    • Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
    • 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM)(256K Bytes)
  • 16K × 16-Bit On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Memory Interface (EMIF) With Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst SRAM (SBSRAM)
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI)
    • Programmable Digital Phase-Locked Loop (DPLL) Clock Generator
    • Eight General-Purpose I/O (GPIO) Pins and Dedicated General-Purpose Output (XF)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (GGW Suffix)
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (ZGW Suffix) [Lead-Free]
  • 3.3-V I/O Supply Voltage
  • 1.6-V Core Supply Voltage

TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.

The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x™;DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.

The C55x™; DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5510/5510A also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.

The 5510/5510A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a 16-bit parallel interface used to provide host processor access to internal memory on the 5510/5510A. The EHPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5510/5510A is supported by the industry’s leading eXpressDSP™; software environment including the Code Composer Studio™; integrated development environment, DSP/BIOS™; software kernel foundation, the TMS320™; DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX™;), XDS510™; emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a pre-emptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’ extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.

Texas Instruments (TI) has also developed foundation software available for the 5510/5510A. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.

The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5510/5510A strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The extensions allow the 5510/5510A to deliver exceptional video codec performance with more than half its bandwidth available for performing additional functions such as color space conversion, user-interface operations, security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5510/5510A DSP can power most portable digital video applications with processing headroom to spare. For more information, see the TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature number SPRU098). For more information on using the the DSP Image Processing Library, see the TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).

The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x™;DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.

The C55x™; DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5510/5510A also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.

The 5510/5510A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a 16-bit parallel interface used to provide host processor access to internal memory on the 5510/5510A. The EHPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5510/5510A is supported by the industry’s leading eXpressDSP™; software environment including the Code Composer Studio™; integrated development environment, DSP/BIOS™; software kernel foundation, the TMS320™; DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX™;), XDS510™; emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a pre-emptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’ extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.

Texas Instruments (TI) has also developed foundation software available for the 5510/5510A. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.

The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5510/5510A strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The extensions allow the 5510/5510A to deliver exceptional video codec performance with more than half its bandwidth available for performing additional functions such as color space conversion, user-interface operations, security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5510/5510A DSP can power most portable digital video applications with processing headroom to spare. For more information, see the TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature number SPRU098). For more information on using the the DSP Image Processing Library, see the TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).

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Technical documentation

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Type Title Date
* Data sheet TMS320VC5510/5510A Fixed-Point Digital Signal Processors datasheet (Rev. O) 24 Sep 2007
* Errata TMS320VC5510A MicroStar BGA Discontinued and Redesigned 22 May 2020
* Errata TMS320VC5510/5510A Digital Signal Processors Silicon Errata (Rev. O) 09 Apr 2008
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 15 Dec 2011
Application note Seismic Sensor Demonstration Using an ADS1255 and TMS320VC5510A DSP (Rev. A) 29 Jan 2009
User guide TMS320VC5503/5507/5509/5510 Direct Memory Access(DMA) Controller Reference Guide (Rev. E) 09 Jan 2007
User guide TMS320VC5503/5507/5509/5510 DSP Timers Reference Guide (Rev. C) 11 Apr 2006
Application note TMS320VC5510/5510A Hardware Designer's Resource Guide (Rev. A) 20 Apr 2005
User guide TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 14 Apr 2005
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 24 Feb 2005
Application note Using the TMS320VC5510 Bootloader (Rev. C) 19 Oct 2004
Application note Using the Power Scaling Library (Rev. A) 30 Sep 2004
User guide TMS320VC5510 DSP Host Port Interface (HPI) Reference Guide (Rev. B) 23 Aug 2004
User guide TMS320VC5510 DSP Instruction Cache Reference Guide (Rev. D) 16 Jun 2004
Application note TMS320VC5510 HPI Throughput and Optimization 27 May 2004
User guide TMS320C55x DSP CPU Reference Guide (Rev. F) 25 Feb 2004
Application note TMS320VC5510 Power Consumption Summary 12 Nov 2003
User guide TMS320VC5510 DSP External Memory Interface (EMIF) Reference Guide 08 Oct 2003
Application note Interfacing TMS320VC5510 to SBSRAM (Rev. A) 16 Jun 2003
Application note Migrating from TMS320VC5510 to TMS320VC5502 28 Feb 2003
User guide TMS320C55x DSP Functional Overview 24 Feb 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Driver or library

SPRC100 — TMS320C55x DSP Library (DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Software codec

C55XCODECS — CODECS - Optimized for C55x Devices

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
Simulation model

VC5510 GGW BSDL Model (Rev. A)

SPRM085A.ZIP (6 KB) - BSDL Model
Simulation model

VC5510 GGW IBIS Model (Rev. A)

SPRM165A.ZIP (67 KB) - IBIS Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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