Product details

Arm CPU 1 Arm9 Arm MHz (Max.) 192 Co-processor(s) C55x DSP CPU 32-bit Hardware accelerators Image/Video Extension Operating system Linux, RTOS Security Cryptography, Device identity, Memory protection Rating Catalog Operating temperature range (C) -40 to 85
Arm CPU 1 Arm9 Arm MHz (Max.) 192 Co-processor(s) C55x DSP CPU 32-bit Hardware accelerators Image/Video Extension Operating system Linux, RTOS Security Cryptography, Device identity, Memory protection Rating Catalog Operating temperature range (C) -40 to 85
NFBGA (ZVL) 289 144 mm² 12.1 x 12.1
  • Low-Power, High-Performance CMOS Technology
    • 0.13-µm Technology
    • 192-MHz Maximum Frequency
    • 1.6 ± 5% V Core Voltage
  • ARM926EJ-S™ (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • Data and Program Memory Management Unit (MMU)
    • 17-Word Write Buffer
    • Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs
  • TMS320C55x™ (C55x™) DSP Core
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Two Multiply-Accumulates per Cycle)
    • Two Arithmetic/Logic Units
    • Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses)
    • 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes)
    • 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes)
    • Instruction Cache (24K Bytes)
    • Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression
  • 250K Bytes of Shared Internal SRAM
  • Memory Traffic Controller (TC)
    • 16-Bit EMIFS Supports up to 256M Bytes of External Memory (i.e., Async. ROM/RAM, NOR/NAND Flash, and Sync. Burst Flash)
    • 16-Bit EMIFF to Access up to 64M Bytes of SDRAM, Mobile SDRAM, or Mobile DDR
  • DSP Memory Management Unit
  • DSP Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • Six-Channel DMA Controller
    • Two Multichannel Buffered Serial Ports
    • Two Multichannel Serial Interfaces
  • MPU Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • USB 1.1 Host and Client Controllers
    • USB On-the-Go (OTG) Controller
    • 3 USB Ports, One With an Integrated Transceiver
    • Camera Interface for Parallel CMOS Sensors
    • Real-Time Clock (RTC)
    • Pulse-Width Tone (PWT) Interface
    • Pulse-Width Light (PWL) Interface
    • Keyboard Matrix Interface (6 x 5 or 8 x 8)
    • HDQ/1-Wire® Interface
    • Multimedia Card (MMC) and Secure Digital (SD) Interface
    • Up to 16 MPU General-Purpose I/Os
    • Two LED Pulse Generators (LPGs)
    • ETM9™ Trace Module for ARM926EJ-S Debug
    • 16-/18-Bit LCD Controller With Dedicated System DMA Channel
    • 32-kHz Operating System (OS) Timer
  • Shared Peripherals
    • 8 General-Purpose Timers
    • Serial Port Interface (SPI)
    • Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting SIR mode for IrDA)
    • Inter-Integrated Circuit (I2C) Master and Slave Interface
    • Multimedia Card (MMC) and Secure Digital (SD) Interface
    • Multichannel Buffered Serial Port
    • Up to 64 Shared General-Purpose I/Os
    • 32-kHz Synchro Counter
  • Endian Conversion Unit
  • Hardware Accelerators for Cryptographic Functions
    • Random Number Generation
    • DES and 3DES
    • SHA-1 and MD5
  • Individual Power-Saving Modes for MPU/DSP/TC
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • Three 289-Ball BGA (Ball Grid Array) Packages (ZDY and ZZG - Lead-Free; GDY - With Lead)
  • The OMAP5912 device is targeted at the following applications:
    • Applications Processing Devices
    • Mobile Communications
      • WAN 802.11X
      • Bluetooth™
      • GSM, GPRS, EDGE
      • CDMA
    • Video and Image Processing (MPEG4, JPEG, Windows® Media Video, etc.)
    • Advanced Speech Applications (text-to-speech, speech recognition)
    • Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and Other GSM Speech Codecs)
    • Graphics and Video Acceleration
    • Generalized Web Access
    • Data Processing

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.


TMS320C55x, C55x, OMAP, and DSP/BIOS are trademarks of Texas Instruments.
ARM926EJ-S and ETM9 are trademarks of ARM Limited in the EU and other countries.
Thumb and ARM are registered trademarks of ARM Limited in the EU and other countries.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.

  • Low-Power, High-Performance CMOS Technology
    • 0.13-µm Technology
    • 192-MHz Maximum Frequency
    • 1.6 ± 5% V Core Voltage
  • ARM926EJ-S™ (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • Data and Program Memory Management Unit (MMU)
    • 17-Word Write Buffer
    • Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs
  • TMS320C55x™ (C55x™) DSP Core
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Two Multiply-Accumulates per Cycle)
    • Two Arithmetic/Logic Units
    • Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses)
    • 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes)
    • 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes)
    • Instruction Cache (24K Bytes)
    • Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression
  • 250K Bytes of Shared Internal SRAM
  • Memory Traffic Controller (TC)
    • 16-Bit EMIFS Supports up to 256M Bytes of External Memory (i.e., Async. ROM/RAM, NOR/NAND Flash, and Sync. Burst Flash)
    • 16-Bit EMIFF to Access up to 64M Bytes of SDRAM, Mobile SDRAM, or Mobile DDR
  • DSP Memory Management Unit
  • DSP Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • Six-Channel DMA Controller
    • Two Multichannel Buffered Serial Ports
    • Two Multichannel Serial Interfaces
  • MPU Peripherals
    • Three 32-Bit Timers and Watchdog Timer
    • USB 1.1 Host and Client Controllers
    • USB On-the-Go (OTG) Controller
    • 3 USB Ports, One With an Integrated Transceiver
    • Camera Interface for Parallel CMOS Sensors
    • Real-Time Clock (RTC)
    • Pulse-Width Tone (PWT) Interface
    • Pulse-Width Light (PWL) Interface
    • Keyboard Matrix Interface (6 x 5 or 8 x 8)
    • HDQ/1-Wire® Interface
    • Multimedia Card (MMC) and Secure Digital (SD) Interface
    • Up to 16 MPU General-Purpose I/Os
    • Two LED Pulse Generators (LPGs)
    • ETM9™ Trace Module for ARM926EJ-S Debug
    • 16-/18-Bit LCD Controller With Dedicated System DMA Channel
    • 32-kHz Operating System (OS) Timer
  • Shared Peripherals
    • 8 General-Purpose Timers
    • Serial Port Interface (SPI)
    • Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting SIR mode for IrDA)
    • Inter-Integrated Circuit (I2C) Master and Slave Interface
    • Multimedia Card (MMC) and Secure Digital (SD) Interface
    • Multichannel Buffered Serial Port
    • Up to 64 Shared General-Purpose I/Os
    • 32-kHz Synchro Counter
  • Endian Conversion Unit
  • Hardware Accelerators for Cryptographic Functions
    • Random Number Generation
    • DES and 3DES
    • SHA-1 and MD5
  • Individual Power-Saving Modes for MPU/DSP/TC
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • Three 289-Ball BGA (Ball Grid Array) Packages (ZDY and ZZG - Lead-Free; GDY - With Lead)
  • The OMAP5912 device is targeted at the following applications:
    • Applications Processing Devices
    • Mobile Communications
      • WAN 802.11X
      • Bluetooth™
      • GSM, GPRS, EDGE
      • CDMA
    • Video and Image Processing (MPEG4, JPEG, Windows® Media Video, etc.)
    • Advanced Speech Applications (text-to-speech, speech recognition)
    • Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and Other GSM Speech Codecs)
    • Graphics and Video Acceleration
    • Generalized Web Access
    • Data Processing

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.


TMS320C55x, C55x, OMAP, and DSP/BIOS are trademarks of Texas Instruments.
ARM926EJ-S and ETM9 are trademarks of ARM Limited in the EU and other countries.
Thumb and ARM are registered trademarks of ARM Limited in the EU and other countries.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.

OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices.

The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC)technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core.

OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices.

The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC)technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core.

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Technical documentation

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Type Title Date
* Data sheet OMAP5912 Applications Processor datasheet (Rev. E) 19 Dec 2005
* Errata OMAP5912 Applications Processor Silicon Errata (Rev. K) 14 Dec 2007
* Errata OMAP59xx MicroStar BGA Discontinued and Redesigned 15 May 2020
* User guide OMAP5912 Technical Reference Guide 15 Sep 2011
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Application note High-Speed Interface Layout Guidelines (Rev. H) 11 Oct 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Analog design journal Enabling high-speed USB OTG functionality on TI DSPs 18 May 2007
User guide OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (Rev. B) 24 Apr 2006
User guide OMAP5912 Multimedia Processor Device Overview and Architecture Reference Guide (Rev. C) 23 Feb 2006
User guide OMAP5912 Multimedia Processor Initialization Reference Guide (Rev. C) 23 Feb 2006
User guide OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (Rev. C) 23 Feb 2006
User guide OMAP5912 Multimedia Processor Memory Interfaces Reference Guide (Rev. C) 24 Jan 2006
User guide OMAP5912 Multimedia Processor Camera Interface Reference Guide (Rev. C) 23 Nov 2005
User guide OMAP5910/5912 Multimedia Processor DSP Subsystem Reference Guide (Rev. A) 17 May 2005
User guide OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support Reference Guide (Rev. C) 28 Mar 2005
Application note OMAP591x: Tuning the System Memory Requirements of DSP/BIOS Link 16 Mar 2005
User guide OMAP5912 Multimedia Processor Multichannel Buffered Serial Ports (McBSPs) RG (Rev. C) 10 Mar 2005
Application note DSP Instruction Cache Performance on the OMAP5912 28 Feb 2005
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 24 Feb 2005
User guide OMAP5910/5912 Applications Processor Timers Reference Guide 22 Feb 2005
Application note Using the CSL to complement OS dispatcher in handling Cascaded Interrupts 08 Nov 2004
User guide OSK5912 Board Design Guide 25 Oct 2004
User guide OMAP5912 Multimedia Processor Display Interface Reference Guide (Rev. B) 14 Oct 2004
User guide OMAP5912 Multimedia Processor Interrupts Reference Guide (Rev. B) 14 Oct 2004
User guide OMAP5912 Multimedia Processor Timers Reference Guide (Rev. B) 14 Oct 2004
Application note Programming the DSP MMU in the OMAP5910 Device 07 Oct 2004
More literature OMAP5912 Product Bulletin 05 Apr 2004
User guide OMAP5912 Multimedia Processor Clocks Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor General-Purpose Interface Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Keyboard Interface Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) Interface Reference (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Peripheral Interconnects Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Power Management Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Real-Time and Split Power Reference Guide (Rev. A) 31 Mar 2004
User guide OMAP5912 Multimedia Processor Universal Serial Bus (USB) Reference Guide (Rev. A) 31 Mar 2004

Design & development

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Debug probe

TMDSADP — Adaptive Clocking JTAG Emulator Adapters

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Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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