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Fixed-Point Digital Signal Processor

TMS320VC5501

ACTIVE

Product details

Parameters

DSP 1 C55x DRAM SDRAM SPI 0 UART (SCI) 1 Serial I/O McBSP, I2C, UART Rating Catalog Operating temperature range (C) -40 to 85 I2C 1 Operating system DSP/BIOS, VLX open-in-new Find other C5000 low-power DSPs

Package | Pins | Size

LQFP (PGF) 176 676 mm² 26 x 26 NFBGA (GBE) 201 225 mm² 15 x 15 NFBGA (ZAV) 201 225 mm² 15 x 15 open-in-new Find other C5000 low-power DSPs

Features

  • High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
    • 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS™ Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/ Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

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Description

The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5501 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio× IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 19
Type Title Date
* Datasheet TMS320VC5501 Fixed-Point Digital Signal Processor datasheet (Rev. K) Nov. 20, 2008
* Errata TMS320VC5501/VC5502 MicroStar BGA Discontinued and Redesigned May 21, 2020
* Errata TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (Rev. L) Jun. 22, 2007
Application note TMS320VC5501, TMS320VC5502 Power Consumption Summary (Rev. A) Dec. 13, 2016
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) Dec. 15, 2011
User guide TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) Oct. 17, 2005
User guide TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (Rev. F) Aug. 22, 2005
User guide TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) Apr. 14, 2005
User guide TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (Rev. G) Mar. 24, 2005
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) Feb. 24, 2005
User guide TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (Rev. D) Nov. 12, 2004
Application note Using the TMS320VC5501/5502 Bootloader (Rev. C) Oct. 19, 2004
Application note TMS320VC5501 Hardware Designer's Resource Guide Jul. 22, 2004
Application note Achieving Efficient Memory System Performance w/ I-Cache on the TMS320VC5501/02 (Rev. A) Jun. 24, 2004
User guide TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C) Jun. 16, 2004
User guide TMS320VC5501/5502 DSP Timers Reference Guide (Rev. B) Apr. 19, 2004
User guide TMS320C55x DSP CPU Reference Guide (Rev. F) Feb. 25, 2004
User guide TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) RG (Rev. B) Dec. 30, 2003
User guide TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) Oct. 11, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
149
Description

The C5502 eZdsp Development Tool is compact, very affordable and offers easy development. The low cost USB-powered DSP development tool which includes all the hardware and software needed to evaluate the industry’s lowest power 16-bit DSP provides more evaluation options such as USB2.0 and SD (...)

Features
Key features and benefits
  • Affordable evaluation and development platform
    • Low-cost eZdsp kit
    • On-board emulation – saves cost of external JTAG emulator
    • Full-featured Code Composer Studio IDE v4 license – for complete application development
  • Ease of use and faster time-to-market
    • Small form factor – about the (...)
DEBUG PROBE Download
Description
The Spectrum Digital XDS100v2 is the second generation of the XDS100 family of debug probes (emulators) for TI processors. The XDS100 family features the lowest cost of all the XDS family of debug probes while supporting the traditional JTAG standard (IEEE1149.1). Also, all XDS debug probes support (...)
Features

The XDS100v2 is the second generation of the XDS100 family of low cost JTAG debug probes (emulators) for TI processors. Designed to deliver full featured JTAG connectivity at a low cost, the XDS100 is the family of choice for entry-level debugging of TI microcontrollers, processors and wireless (...)

DEBUG PROBE Download
XDS200 USB Debug Probe
TMDSEMU200-U
295
Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBE Download
995
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBE Download
1495
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

DRIVER OR LIBRARY Download
TMS320C55x DSP Library (DSPLIB)
SPRC100 The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
DRIVER OR LIBRARY Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
Code Composer Studio (CCS) Integrated Development Environment (IDE)
CCSTUDIO

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

SOFTWARE CODEC Download
CODECS - Optimized for C55x Devices
C55XCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
Features

C55x Codecs are optimized for use on any TM320C55x™ devices. C55x Codecs offer:

  • Free, object code with production licensing
  • WINDOWS installers
  • C55x Audio Codecs were tested on C5505 and C5510 devices
  • C55x Speech Codecs were tested on C5510 device
  • All codecs are eXpressDSP™ compliant
  • Performance data are (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM158.ZIP (6 KB) - BSDL Model
SIMULATION MODEL Download
SPRM159.ZIP (6 KB) - BSDL Model
SIMULATION MODEL Download
SPRM160.ZIP (106 KB) - IBIS Model
SIMULATION MODEL Download
SPRM161.ZIP (106 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR (GZZ) 201 View options
BGA MICROSTAR (ZZZ) 201 View options
LQFP (PGF) 176 View options
NFBGA (GBE) 201 View options
NFBGA (ZAV) 201 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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