Low power C55x fixed point DSP- up to 300MHz

TMS320VC5501

ACTIVE

Product details

DSP 1 C55x DSP MHz (Max) 300 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85
DSP 1 C55x DSP MHz (Max) 300 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (C) -40 to 85
LQFP (PGF) 176 676 mm² 26 x 26 NFBGA (GBE) 201 225 mm² 15 x 15 NFBGA (ZAV) 201 225 mm² 15 x 15
  • High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
    • 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS™ Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/ Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

  • High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
    • 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
    • 16K-Byte Instruction Cache (I-Cache)
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
  • Instruction Cache (16K Bytes)
  • 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
  • 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst RAM (SBRAM)
  • Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Six-Channel Direct Memory Access (DMA) Controller
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Analog Phase-Locked Loop (APLL) Clock Generator
    • General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
    • 8-Bit Parallel Host-Port Interface (HPI)
    • Four Timers
      • Two 64-Bit General-Purpose Timers
      • 64-Bit Programmable Watchdog Timer
      • 64-Bit DSP/BIOS™ Counter
    • Inter-Integrated Circuit (I2C) Interface
    • Universal Asynchronous Receiver/ Transmitter (UART)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
    • 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)
  • 3.3-V I/O Supply Voltage
  • 1.26-V Core Supply Voltage

TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).

The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5501 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio× IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 5501 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Two full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is an 8-bit parallel interface used to provide host processor access to 16K words of internal memory on the 5501. The HPI operates in multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included.

The 5501 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio× IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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Technical documentation

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Type Title Date
* Data sheet TMS320VC5501 Fixed-Point Digital Signal Processor datasheet (Rev. K) 20 Nov 2008
* Errata TMS320VC5501/VC5502 MicroStar BGA Discontinued and Redesigned 21 May 2020
* Errata TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (Rev. L) 22 Jun 2007
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Application note TMS320VC5501, TMS320VC5502 Power Consumption Summary (Rev. A) 13 Dec 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 15 Dec 2011
User guide TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) 17 Oct 2005
User guide TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (Rev. F) 22 Aug 2005
User guide TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 14 Apr 2005
User guide TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (Rev. G) 24 Mar 2005
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 24 Feb 2005
User guide TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (Rev. D) 12 Nov 2004
Application note Using the TMS320VC5501/5502 Bootloader (Rev. C) 19 Oct 2004
Application note TMS320VC5501 Hardware Designer's Resource Guide 22 Jul 2004
Application note Achieving Efficient Memory System Performance w/ I-Cache on the TMS320VC5501/02 (Rev. A) 24 Jun 2004
User guide TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C) 16 Jun 2004
User guide TMS320VC5501/5502 DSP Timers Reference Guide (Rev. B) 19 Apr 2004
User guide TMS320C55x DSP CPU Reference Guide (Rev. F) 25 Feb 2004
User guide TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) RG (Rev. B) 30 Dec 2003
User guide TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) 11 Oct 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TMDX5502EZDSP — C5502 eZdsp Development Kit

The C5502 eZdsp Development Tool is compact, very affordable and offers easy development. The low cost USB-powered DSP development tool which includes all the hardware and software needed to evaluate the industry’s lowest power 16-bit DSP provides more evaluation options such as USB2.0 and SD (...)

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Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Limit: 1
Driver or library

SPRC100 — TMS320C55x DSP Library (DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Software codec

C55XCODECS — CODECS - Optimized for C55x Devices

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)
Simulation model

C5501 PGF BSDL Model

SPRM158.ZIP (6 KB) - BSDL Model
Simulation model

C5501 GZZ BSDL Model

SPRM159.ZIP (6 KB) - BSDL Model
Simulation model

C5501 PGF IBIS Model

SPRM160.ZIP (106 KB) - IBIS Model
Simulation model

C5501 GZZ IBIS Model

SPRM161.ZIP (106 KB) - IBIS Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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NFBGA (ZAV) 201 View options

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