Product details

Number of channels (#) 2 Power switch MOSFET, IGBT, GaNFET Peak output current (A) 5 Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 18 Features Negative Voltage Handling on Input Operating temperature range (C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Prop delay (ns) 17 Input threshold CMOS Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Catalog Undervoltage lockout (Typ) 4 Driver configuration Dual, Non-Inverting
Number of channels (#) 2 Power switch MOSFET, IGBT, GaNFET Peak output current (A) 5 Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 18 Features Negative Voltage Handling on Input Operating temperature range (C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Prop delay (ns) 17 Input threshold CMOS Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Catalog Undervoltage lockout (Typ) 4 Driver configuration Dual, Non-Inverting
SOIC (D) 8 19 mm² 4.9 x 3.9 WSON (DSD) 8 9 mm² 3 x 3
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink Drive Current
  • CMOS Input Logic Threshold (Function of
    Supply Voltage on VDD Pins)
  • Hysteretic Logic Thresholds for High Noise
    Immunity
  • Independent Enable Function for Each Output
  • Inputs and Enable Pin Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (Ensures
    Glitch-Free Operation at Power Up and Power
    Down)
  • Fast Propagation Delays (17-ns Typical)
  • Fast Rise and Fall Times (7-ns and 6-ns Typical)
  • 1-ns Typical Delay Matching Between 2 Channels
  • Outputs Held in Low When Inputs Floating
  • SOIC-8, and 3-mm × 3-mm WSON-8 Package Options
  • Operating Temperature Range of –40°C to 140°C
  • –5-V Negative Voltage Handling Capability on Input Pins
  • Industry-Standard Pin Out
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink Drive Current
  • CMOS Input Logic Threshold (Function of
    Supply Voltage on VDD Pins)
  • Hysteretic Logic Thresholds for High Noise
    Immunity
  • Independent Enable Function for Each Output
  • Inputs and Enable Pin Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (Ensures
    Glitch-Free Operation at Power Up and Power
    Down)
  • Fast Propagation Delays (17-ns Typical)
  • Fast Rise and Fall Times (7-ns and 6-ns Typical)
  • 1-ns Typical Delay Matching Between 2 Channels
  • Outputs Held in Low When Inputs Floating
  • SOIC-8, and 3-mm × 3-mm WSON-8 Package Options
  • Operating Temperature Range of –40°C to 140°C
  • –5-V Negative Voltage Handling Capability on Input Pins

The UCC2752x family of devices are dual-channel, high-speed, low-side gate driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 17 ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The Enable pins are based on TTL and CMOS compatible logic, independent of VDD supply voltage.

The UCC27528 is a dual noninverting driver. UCC27527 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family to ensure that outputs are held low when input pins are in floating condition. UCC27528 features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active high logic and can be left open for standard operation.

The UCC2752x family of devices are dual-channel, high-speed, low-side gate driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 17 ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The Enable pins are based on TTL and CMOS compatible logic, independent of VDD supply voltage.

The UCC27528 is a dual noninverting driver. UCC27527 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family to ensure that outputs are held low when input pins are in floating condition. UCC27528 features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active high logic and can be left open for standard operation.

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Technical documentation

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Type Title Date
* Data sheet UCC2752x Dual 5-A High-Speed Low-Side Gate Driver Based on CMOS Input Threshold Logic datasheet (Rev. E) PDF | HTML 05 Dec 2014
Technical article Managing power-supply noise with a 30-V gate driver 07 Dec 2021
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Application note Improving Efficiency of DC-DC Conversion through Layout 07 May 2019
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC27423-4-5-Q1EVM — UCC2742xQ1 Dual 4-A High-Speed Low-Side MOSFET Drivers With Enable Evaluation Module (EVM)

The UCC2742xQ1 EVM is a high-speed dual MOSFET evaluation module that provides a test platform for a quick and easy startup of the UCC2742xQ1 driver. Powered by a single 4V to 15V external supply, and featuring a comprehensive set of test points and jumpers. All of the devices have separate input (...)
Not available on TI.com
Simulation model

UCC27528 PSpice Transient Model

SLUM344.ZIP (49 KB) - PSpice Model
Simulation model

UCC27528 Unencrypted PSpice Transient Model

SLUM480.ZIP (2 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

UCC2752X Schematic Review Template

SLURB22.ZIP (110 KB)
Package Pins Download
SOIC (D) 8 View options
SON (DSD) 8 View options

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