Product details

Number of channels (#) 1 Power switch MOSFET, GaNFET Peak output current (A) 6 Input VCC (Min) (V) 4 Input VCC (Max) (V) 18 Features Split Output, Regulated gate driver voltage Operating temperature range (C) -40 to 140 Rise time (ns) 9 Fall time (ns) 4 Prop delay (ns) 14 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (Typ) 8
Number of channels (#) 1 Power switch MOSFET, GaNFET Peak output current (A) 6 Input VCC (Min) (V) 4 Input VCC (Max) (V) 18 Features Split Output, Regulated gate driver voltage Operating temperature range (C) -40 to 140 Rise time (ns) 9 Fall time (ns) 4 Prop delay (ns) 14 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (Typ) 8
WSON (DRV) 6 4 mm² 2 x 2
  • Enhancement Mode Gallium Nitride FETs (eGANFETs)
  • 4-V to 18-V Single Supply Range VDD Range
  • Drive Voltage VREF Regulated to 5 V
  • 4-A Peak Source and 6-A Peak Sink Drive Current
  • 1-Ω and 0.35-Ω Pullup and Pulldown Resistance (Maximize High Slew-Rate dV and dt Immunity)
  • Split Output Configuration (Allows Turnon and Turnoff Optimization for Individual FETs)
  • Fast Propagation Delays (14-ns Typical)
  • Fast Rise and Fall Times (9-ns and 5-ns Typical)
  • TTL and CMOS Compatible Inputs (Independent of Supply Voltage Allow Easy Interface-to-Digital and Analog Controllers)
  • Dual-Input Design Offering Drive Flexibility (Both Inverting and Noninverting Configurations)
  • Output Held Low When Inputs Are Floating
  • VDD Under Voltage Lockout (UVLO)
  • Optimized Pinout Compatible With eGANFET Footprint for Easy Layout
  • 2.00 mm × 2.00 mm SON-6 Package With Exposed Thermal and Ground Pad, (Minimized Parasitic Inductances to Reduce Gate Ringing)
  • Operating Temperature Range of –40°C to 140°C
  • Enhancement Mode Gallium Nitride FETs (eGANFETs)
  • 4-V to 18-V Single Supply Range VDD Range
  • Drive Voltage VREF Regulated to 5 V
  • 4-A Peak Source and 6-A Peak Sink Drive Current
  • 1-Ω and 0.35-Ω Pullup and Pulldown Resistance (Maximize High Slew-Rate dV and dt Immunity)
  • Split Output Configuration (Allows Turnon and Turnoff Optimization for Individual FETs)
  • Fast Propagation Delays (14-ns Typical)
  • Fast Rise and Fall Times (9-ns and 5-ns Typical)
  • TTL and CMOS Compatible Inputs (Independent of Supply Voltage Allow Easy Interface-to-Digital and Analog Controllers)
  • Dual-Input Design Offering Drive Flexibility (Both Inverting and Noninverting Configurations)
  • Output Held Low When Inputs Are Floating
  • VDD Under Voltage Lockout (UVLO)
  • Optimized Pinout Compatible With eGANFET Footprint for Easy Layout
  • 2.00 mm × 2.00 mm SON-6 Package With Exposed Thermal and Ground Pad, (Minimized Parasitic Inductances to Reduce Gate Ringing)
  • Operating Temperature Range of –40°C to 140°C

The UCC27611 is a single-channel, high-speed, gate driver optimized for 5-V drive, specifically addressing enhancement mode GaN FETs. The drive voltage VREF is precisely controlled by internal linear regulator to 5 V. The UCC27611 offers asymmetrical rail-to-rail peak current drive capability with 4-A source and 6-A sink. Split output configuration allows individual turnon and turnoff time optimization depending on FET. Package and pinout with minimum parasitic inductances reduce the rise and fall time and limit the ringing. Additionally, the short propagation delay with minimized tolerances and variations allows efficient operation at high frequencies. The 1-Ω and 0.35-Ω resistance boosts immunity to hard switching with high slew rate dV and dt.

The independence from VDD input signal thresholds ensure TTL and CMOS low-voltage logic compatibility. For safety reason, when the input pins are in a floating condition, the internal input pullup and pulldown resistors hold the output LOW. Internal circuitry on VREF pin provides an undervoltage lockout function that holds output LOW until VREF supply voltage is within operating range. UCC27611 is offered in a small 2.00 mm × 2.00 mm SON-6 package (DRV) with exposed thermal and ground pad that improves the package power-handling capability. The UCC27611 operates over wide temperature range from –40°C to 140°C.

The UCC27611 is a single-channel, high-speed, gate driver optimized for 5-V drive, specifically addressing enhancement mode GaN FETs. The drive voltage VREF is precisely controlled by internal linear regulator to 5 V. The UCC27611 offers asymmetrical rail-to-rail peak current drive capability with 4-A source and 6-A sink. Split output configuration allows individual turnon and turnoff time optimization depending on FET. Package and pinout with minimum parasitic inductances reduce the rise and fall time and limit the ringing. Additionally, the short propagation delay with minimized tolerances and variations allows efficient operation at high frequencies. The 1-Ω and 0.35-Ω resistance boosts immunity to hard switching with high slew rate dV and dt.

The independence from VDD input signal thresholds ensure TTL and CMOS low-voltage logic compatibility. For safety reason, when the input pins are in a floating condition, the internal input pullup and pulldown resistors hold the output LOW. Internal circuitry on VREF pin provides an undervoltage lockout function that holds output LOW until VREF supply voltage is within operating range. UCC27611 is offered in a small 2.00 mm × 2.00 mm SON-6 package (DRV) with exposed thermal and ground pad that improves the package power-handling capability. The UCC27611 operates over wide temperature range from –40°C to 140°C.

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Technical documentation

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Type Title Date
* Data sheet UCC27611 5-V, 4-A to 6-A Low Side GaN Driver datasheet (Rev. F) 12 Mar 2018
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Application note Enable Function with Unused Differential Input 11 Jul 2018
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018
White paper A comprehensive methodology to qualify the reliability of GaN products 02 Mar 2015
White paper Advancing Power Supply Solutions Through the Promise of GaN 24 Feb 2015
User guide Using the UCC27611OLEVM-203 29 Nov 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMG1020EVM-006 — LMG1020 GaN Low-side Driver + GaN FET LiDAR Evaluation Module

The LMG1020EVM-006 is a small, easy-to-use power stage for LIDAR laser drive. The EVM includes an integrated resistive load, (laser not included) and takes a short-pulse input that can either be buffered (and shortened further), or passed directly to the power stage. The board can demonstrate (...)
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Evaluation board

UCC27611OLEVM-203 — UCC27611 Gate Driver Open Loop Evaluation Module

The UCC27611OLEVM-203 aids in the evaluation of high-speed, single channel, low-side driver capable of driving eGANFETs with a regulated 5-V optimized output. The EVM is designed to drive a capacitive load on the output of the UCC27611 device, with connectors provided to offer flexibility to bring (...)
In stock
Limit: 3
Simulation model

UCC27611 PSpice Transient Model (Rev. C)

SLUM339C.ZIP (45 KB) - PSpice Model
Simulation model

UCC27611 TINA-TI Transient Reference Design (Rev. E)

SLUM362E.TSC (761 KB) - TINA-TI Reference Design
Simulation model

UCC27611 TINA-TI Transient Spice Model (Rev. B)

SLUM363B.ZIP (5 KB) - TINA-TI Spice Model
Simulation model

UCC27611 Unencrypted PSpice Transient Model (Rev. B)

SLUM487B.ZIP (2 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00785 — Isolated GaN Driver Reference Design

This reference design consists of a reinforced dualchannel digital isolator, a GaN gate driver, and isolated power supplies. This compact reference design is intended to control GaN in power supplies, DC-to-DC converters, synchronous rectification, solar inverters, and motor control. An open-loop (...)
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WSON (DRV) 6 View options

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