Product details


Type Bridge Protocols PCIe Applications PCIe Supply voltage (V) 1.5, 3.3 Rating Catalog Operating temperature range (C) -40 to 85, 0 to 70 open-in-new Find other PCIe, SAS & SATA ICs

Package | Pins | Size

HTQFP (PNP) 128 256 mm² 16 x 16 NFBGA (ZAJ) 144 49 mm² 7 x 7 NFBGA (ZWS) 169 144 mm² 12 x 12 open-in-new Find other PCIe, SAS & SATA ICs


  • Full ×1 PCI Express™ Throughput
  • Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
  • Fully Compliant With PCI Express Base Specification, Revision 2.0
  • Fully Compliant With PCI Local Bus Specification, Revision 2.3
  • PCI Express Advanced Error Reporting Capability Including ECRC Support
  • Support for D1, D2, D3hot, and D3cold
  • Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
  • Wake Event and Beacon Support
  • Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
  • Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
  • Optional Spread Spectrum Reference Clock is Supported
  • Robust Pipeline Architecture to Minimize Transaction Latency
  • Full PCI Local Bus 66-MHz/32-Bit Throughput
  • Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
  • Internal PCI Arbiter Supporting Up to 6 External PCI Masters
  • Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
  • External PCI Bus Arbiter Option
  • PCI Bus LOCK Support
  • JTAG/BS for Production Test
  • PCI-Express CLKREQ Support
  • Clock Run and Power Override Support
  • Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
  • PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
  • Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
  • Five 3.3-V, Multifunction, General-Purpose I/O Terminals
  • Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
  • Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package

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The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet XIO2001 PCIe to PCI Bus Translation Bridge datasheet (Rev. J) Dec. 06, 2020
* Errata XIO2001 Errata (Rev. B) Dec. 17, 2012
Application note XIO2001 Implementation Guide. (Rev. D) Jun. 19, 2014
User guide XIO2001 EVM User Guide (Rev. B) Jun. 12, 2014
Application note XIO2000A to XIO2001 Change Document May 28, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The XIO2001EVM evaluation module (EVM) implements a peripheral component interconnect (PCI) express to PCI bridge circuit using the Texas Instruments XIO2001 PCI Express® (PCIe) to PCI bus translation bridge. Designed as a half-width x1 PCIe add-in card, the EVM provides you with 3 standard PCI slots.

  • Full-featured evaluation board for the XIO2001 PCIe to PCI bus translation bridge
  • Designed to work directly out of the box with no driver needed
  • On-board EEPROM programmed with values that let the EVM function in most systems
  • XIO2001 performance tuning software provides you with the ability to easily (...)

Software development

SCPC009A.ZIP (3444 KB)

Design tools & simulation

SCPM016.ZIP (96 KB) - IBIS Model
SCPM017.ZIP (96 KB) - IBIS Model
SCPM019A.ZIP (4 KB) - BSDL Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR (ZGU) 169 View options
HTQFP (PNP) 128 View options
NFBGA (ZAJ) 144 View options
NFBGA (ZWS) 169 View options

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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