XIO2001

HTQFP (PNP)

128

256 mm² 16 x 16

NFBGA (ZAJ)

144

49 mm² 7 x 7

NFBGA (ZWS)

169

144 mm² 12 x 12

Full ×1 PCI Express™ Throughput
Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
Fully Compliant With PCI Express Base Specification, Revision 2.0
Fully Compliant With PCI Local Bus Specification, Revision 2.3
PCI Express Advanced Error Reporting Capability Including ECRC Support
Support for D1, D2, D3_hot, and D3_cold
Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
Wake Event and Beacon Support
Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
Optional Spread Spectrum Reference Clock is Supported
Robust Pipeline Architecture to Minimize Transaction Latency
Full PCI Local Bus 66-MHz/32-Bit Throughput
Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
Internal PCI Arbiter Supporting Up to 6 External PCI Masters
Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
External PCI Bus Arbiter Option
PCI Bus LOCK Support
JTAG/BS for Production Test
PCI-Express CLKREQ Support
Clock Run and Power Override Support
Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
Integrated AUX Power Switch Drains V_AUX Power Only When Main Power Is Off
Five 3.3-V, Multifunction, General-Purpose I/O Terminals
Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package

Full ×1 PCI Express™ Throughput
Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
Fully Compliant With PCI Express Base Specification, Revision 2.0
Fully Compliant With PCI Local Bus Specification, Revision 2.3
PCI Express Advanced Error Reporting Capability Including ECRC Support
Support for D1, D2, D3_hot, and D3_cold
Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
Wake Event and Beacon Support
Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
Optional Spread Spectrum Reference Clock is Supported
Robust Pipeline Architecture to Minimize Transaction Latency
Full PCI Local Bus 66-MHz/32-Bit Throughput
Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
Internal PCI Arbiter Supporting Up to 6 External PCI Masters
Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
External PCI Bus Arbiter Option
PCI Bus LOCK Support
JTAG/BS for Production Test
PCI-Express CLKREQ Support
Clock Run and Power Override Support
Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
Integrated AUX Power Switch Drains V_AUX Power Only When Main Power Is Off
Five 3.3-V, Multifunction, General-Purpose I/O Terminals
Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.

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Technical documentation

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	Type	Title	Date
*	Data sheet	XIO2001 PCIe to PCI Bus Translation Bridge datasheet (Rev. J)	06 Dec 2020
*	Errata	XIO2001 Errata (Rev. B)	17 Dec 2012
	Application note	XIO2001 Implementation Guide. (Rev. D)	19 Jun 2014
	User guide	XIO2001 EVM User Guide (Rev. B)	12 Jun 2014
	Application note	XIO2000A to XIO2001 Change Document	28 May 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

XIO2001EVM — XIO2001 evaluation module

The XIO2001EVM evaluation module (EVM) implements a peripheral component interconnect (PCI) express to PCI bridge circuit using the Texas Instruments XIO2001 PCI Express® (PCIe) to PCI bus translation bridge. Designed as a half-width x1 PCIe add-in card, the EVM provides you with 3 standard PCI slots.

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User guide

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Support software

XIO2001 Performance Tuner (Rev. A)

SCPC009A.ZIP (3444 KB)

Simulation model

IBIS Model of XIO2001 (ZGU Package)

SCPM016.ZIP (96 KB) - IBIS Model

Simulation model

IBIS Model of XIO2001 (ZAJ Package)

SCPM017.ZIP (96 KB) - IBIS Model

Simulation model

XIO2001 BSDL Model (Rev. A)

SCPM019A.ZIP (4 KB) - BSDL Model