Produktdetails

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 20 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family ACT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 20 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family ACT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines Directly
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines Directly
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The 'ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The 'ACT16861 can be used as two 10-bit transceivers or one 20-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (or ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The 74ACT16861 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16861 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16861 is characterized for operation from -40°C to 85°C.

 

 

The 'ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The 'ACT16861 can be used as two 10-bit transceivers or one 20-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (or ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The 74ACT16861 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16861 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16861 is characterized for operation from -40°C to 85°C.

 

 

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 20-Bit Bus Transceivers With 3-State Outputs datasheet (Rev. B) 01 Nov 1996
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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SSOP (DL) 56 Ultra Librarian

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