Produktdetails

Sample rate (max) (Msps) 200 Resolution (bps) 11 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 900 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 473 Architecture Pipeline SNR (dB) 63.8 ENOB (bit) 10.06 SFDR (dB) 82.4 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 200 Resolution (bps) 11 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 900 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 1.5 Power consumption (typ) (mW) 473 Architecture Pipeline SNR (dB) 63.8 ENOB (bit) 10.06 SFDR (dB) 82.4 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (NKA) 60 81 mm² 9 x 9
  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2's Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.

Key Specifications

  • Resolution: 11 Bits
  • Conversion Rate: 200 MSPS
  • ENOB: 10.06 bits (typ) @Fin=70 MHz
  • SNR: 62.5 dBFS (typ) @Fin=70 MHz
  • SINAD: 62.3 dBFS (typ) @Fin=70 MHz
  • SFDR: 82 dBFS (typ) @Fin=70 MHz
  • LVDS: Power 450 mW (typ) @Fs=200 MSPS
  • CMOS: Power 280 mW (typ) @Fs=170 MSPS
  • Operating Temp. Range: −40°C to +85°C.

All trademarks are the property of their respective owners.

  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2's Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.

Key Specifications

  • Resolution: 11 Bits
  • Conversion Rate: 200 MSPS
  • ENOB: 10.06 bits (typ) @Fin=70 MHz
  • SNR: 62.5 dBFS (typ) @Fin=70 MHz
  • SINAD: 62.3 dBFS (typ) @Fin=70 MHz
  • SFDR: 82 dBFS (typ) @Fin=70 MHz
  • LVDS: Power 450 mW (typ) @Fs=200 MSPS
  • CMOS: Power 280 mW (typ) @Fs=170 MSPS
  • Operating Temp. Range: −40°C to +85°C.

All trademarks are the property of their respective owners.

The ADC11DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 11-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC11DV200 may be operated from a single 1.8V power supply. The ADC11DV200 achieves approximately 10.06 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.

The ADC11DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 11-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC11DV200 may be operated from a single 1.8V power supply. The ADC11DV200 achieves approximately 10.06 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 2
Typ Titel Datum
* Data sheet Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs datasheet (Rev. A) 02 Apr 2013
User guide ADC10/11DV200, 10/11-Bit, 200 Msps A/D Converter User Guide 20 Feb 2012

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese voll ausgestattete Design- und Simulationssuite verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
WQFN (NKA) 60 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos