The ADC12DL3200 is an RF-sampling, giga-sample,
analog-to-digital converter (ADC) that can
directly sample input frequencies from DC to above
10 GHz. In dual-channel mode, the ADC12DL3200 can
sample up to 3200 MSPS and in single-channel mode
up to 6400 MSPS. Programmable tradeoffs in channel
count (dual-channel mode) and Nyquist bandwidth
(single-channel mode) allow development of
flexible hardware that meets the needs of both
high-channel count or wide instantaneous signal
bandwidth applications. Full-power input bandwidth
(–3 dB) of 8.0 GHz and a useable frequency range
allows direct RF sampling of L-band, S-band,
C-band, and X-band for frequency agile
systems.
The ADC12DL3200 uses a low-latency, low-voltage
differential signaling (LVDS) interface for
latency sensitive applications or when the
simplicity of LVDS is preferred. The interface
uses up to 48 data pairs, four double data rate
(DDR) clocks, and four strobe signals arranged in
four 12-bit data buses. The interface supports
signaling rates of up to 1.6 Gbps. Strobe signals
simplify synchronization across buses and between
multiple devices. The strobe is generated
internally and can be reset at a deterministic
time by the SYSREF input. Multi-device
synchronization is further eased by innovative
synchronization features such as noiseless
aperture delay (T AD) adjustment and
SYSREF windowing.
The ADC12DL3200 is an RF-sampling, giga-sample,
analog-to-digital converter (ADC) that can
directly sample input frequencies from DC to above
10 GHz. In dual-channel mode, the ADC12DL3200 can
sample up to 3200 MSPS and in single-channel mode
up to 6400 MSPS. Programmable tradeoffs in channel
count (dual-channel mode) and Nyquist bandwidth
(single-channel mode) allow development of
flexible hardware that meets the needs of both
high-channel count or wide instantaneous signal
bandwidth applications. Full-power input bandwidth
(–3 dB) of 8.0 GHz and a useable frequency range
allows direct RF sampling of L-band, S-band,
C-band, and X-band for frequency agile
systems.
The ADC12DL3200 uses a low-latency, low-voltage
differential signaling (LVDS) interface for
latency sensitive applications or when the
simplicity of LVDS is preferred. The interface
uses up to 48 data pairs, four double data rate
(DDR) clocks, and four strobe signals arranged in
four 12-bit data buses. The interface supports
signaling rates of up to 1.6 Gbps. Strobe signals
simplify synchronization across buses and between
multiple devices. The strobe is generated
internally and can be reset at a deterministic
time by the SYSREF input. Multi-device
synchronization is further eased by innovative
synchronization features such as noiseless
aperture delay (T AD) adjustment and
SYSREF windowing.