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ADC3664-SP

AKTIV

Radiation-hardened, QML-V, 300krad, 14-bit dual 125MSPS ADC

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Datenblatt

ADC3664-SP

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 200 Features Bypass Mode, Decimating Filter, Differential Inputs, Dual Channel, High Dynamic Range, High Performance, Internal Reference, LVDS interface, Low latency, Low power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 200 Architecture SAR SNR (dB) 78 ENOB (Bits) 12.6 SFDR (dB) 84 Operating temperature range (°C) -40 to 105 Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 200 Features Bypass Mode, Decimating Filter, Differential Inputs, Dual Channel, High Dynamic Range, High Performance, Internal Reference, LVDS interface, Low latency, Low power Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 200 Architecture SAR SNR (dB) 78 ENOB (Bits) 12.6 SFDR (dB) 84 Operating temperature range (°C) -40 to 105 Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
CFP (HBP) 64 862.0096 mm² (29.36 mm × 29.36 mm)
  • Screening and radiation performance
    • QMLV screening and reliability assurance
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: -55°C to 105°C
  • Dual Channel ADC
  • 14-bit 125MSPS
  • Noise floor: -156.9dBFS/Hz
  • Low power consumption: 100mW/ch
  • Latency: 2 clock cycles
  • Clock rate versus voltage reference:
    • External reference: 1MSPS to 125MSPS
    • Internal reference: 100MSPS to 125MSPS
  • 14-Bit, no missing codes
  • Input bandwidth: 200MHz (-3dB)
  • INL: ±2.6LSB; DNL: ±0.9LSB
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 77.5dBFS
    • SFDR: 84dBc HD2, HD3
    • Non HD23: 91dBc
  • Screening and radiation performance
    • QMLV screening and reliability assurance
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: -55°C to 105°C
  • Dual Channel ADC
  • 14-bit 125MSPS
  • Noise floor: -156.9dBFS/Hz
  • Low power consumption: 100mW/ch
  • Latency: 2 clock cycles
  • Clock rate versus voltage reference:
    • External reference: 1MSPS to 125MSPS
    • Internal reference: 100MSPS to 125MSPS
  • 14-Bit, no missing codes
  • Input bandwidth: 200MHz (-3dB)
  • INL: ±2.6LSB; DNL: ±0.9LSB
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 77.5dBFS
    • SFDR: 84dBc HD2, HD3
    • Non HD23: 91dBc

The ADC3664-SP is a low latency, low noise, and ultra low power, 14-bit, 125MSPS, high-speed dual channel ADC. Designed for best noise performance, the device delivers a noise spectral density of –156.9dBFS/Hz combined with excellent linearity and dynamic range. The ADC3664-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 100mW/ch at 125MSPS and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The device is pin-to-pin compatible with the 18-bit, 65MSPS ADC3683-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm) and supports a temperature range from –55°C to +105°C.

The ADC3664-SP is a low latency, low noise, and ultra low power, 14-bit, 125MSPS, high-speed dual channel ADC. Designed for best noise performance, the device delivers a noise spectral density of –156.9dBFS/Hz combined with excellent linearity and dynamic range. The ADC3664-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 100mW/ch at 125MSPS and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The device is pin-to-pin compatible with the 18-bit, 65MSPS ADC3683-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm) and supports a temperature range from –55°C to +105°C.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt ADC3664-SP Radiation-Hardness-Assured 14-Bit, Dual Channel, 1 to 125MSPS, Low Latency, Low Noise, Ultra-low Power, Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 08.04.2025
* Strahlungs- und Zuverlässigkeitsbericht ADC3664-SP Total Ionizing Dose (TID) Radiation Report 19.03.2025

Design und Entwicklung

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Evaluierungsplatine

ADC3664EVMCVAL — ADC3664-SP – Evaluierungsmodul

Das ADC3664-Evaluierungsmodul (EVM) wurde entwickelt, um den ADC3664-SP Hochgeschwindigkeits-Analog-Digital-Wandler (ADC) auszuwerten. Das EVM ist mit dem ADC3664-SP bestückt, einem 18-Bit, Dual-Channel 125 MSPS Hochgeschwindigkeits-Analog-Digital-Wandler (ADC) mit serieller LVDS-Schnittstelle.
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ADC3683-SP IBIS Model

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