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AM625-Q1

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AM625-Q1

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Produktdetails

CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-M4F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols Ethernet, TSN Features Vision Analytics Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65219 Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-M4F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols Ethernet, TSN Features Vision Analytics Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65219 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (AMC) 441 295.84 mm² 17.2 x 17.2 FCCSP (ALW) 425 169 mm² 13 x 13

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm® Cortex®-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device/Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 165MHz pixel clock support with Independent PLL for each display
    • OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS)
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500Mpixels/sec
    • >500MTexels/s, >8GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
    • Max addressable range
      • 8GBytes with DDR4
      • 4GBytes with LPDDR4

Functional Safety:

  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TUV SUD planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU with SECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory with SECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of 30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16nm technology
  • 13mm x 13mm, 0.5mm pitch, 425-pin FCCSP BGA (ALW)
  • 17.2mm x 17.2mm, 0.8mm pitch, 441-pin FCBGA (AMC)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm® Cortex®-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device/Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 165MHz pixel clock support with Independent PLL for each display
    • OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS)
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500Mpixels/sec
    • >500MTexels/s, >8GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
    • Max addressable range
      • 8GBytes with DDR4
      • 4GBytes with LPDDR4

Functional Safety:

  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TUV SUD planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit Subystem (PRUSS) running up to 333MHz
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU with SECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory with SECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of 30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16nm technology
  • 13mm x 13mm, 0.5mm pitch, 425-pin FCCSP BGA (ALW)
  • 17.2mm x 17.2mm, 0.8mm pitch, 441-pin FCBGA (AMC)

The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as dual-display support and 3D graphics acceleration, along with an extensive set of peripherals, making the AM62x device well-suited for a broad range of industrial and automotive applications while offering intelligent features and optimized power architecture.

Functional safety requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all be isolated from the rest of the AM62x processor.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) capable. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM62x enable system-level connectivity, such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications.

Products in the AM62x processor family:

  • AM625 – Human-machine Interaction SoC with Arm® Cortex®-A53-based edge AI and full-HD dual-display
  • AM625-Q1 – Automotive Display SoC with embedded safety for digital clusters
  • AM623 – Internet of Things (IoT) and Gateway SoC with Arm® Cortex®-A53-based object and gesture recognition
  • AM620-Q1 – Automotive Compute SoC with embedded safety for driver monitoring, networking and V2X systems

The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as dual-display support and 3D graphics acceleration, along with an extensive set of peripherals, making the AM62x device well-suited for a broad range of industrial and automotive applications while offering intelligent features and optimized power architecture.

Functional safety requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all be isolated from the rest of the AM62x processor.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) capable. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM62x enable system-level connectivity, such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications.

Products in the AM62x processor family:

  • AM625 – Human-machine Interaction SoC with Arm® Cortex®-A53-based edge AI and full-HD dual-display
  • AM625-Q1 – Automotive Display SoC with embedded safety for digital clusters
  • AM623 – Internet of Things (IoT) and Gateway SoC with Arm® Cortex®-A53-based object and gesture recognition
  • AM620-Q1 – Automotive Compute SoC with embedded safety for driver monitoring, networking and V2X systems
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet AM62x Sitara™ Processors datasheet (Rev. C) PDF | HTML 31 Okt 2025
* Errata AM62x Sitara Errata (Rev. G) PDF | HTML 30 Okt 2025
* User guide AM62x Sitara Processors Technical Reference Manual (Rev. C) PDF | HTML 29 Dez 2025
White paper Securing the Future: Cyber Resilience Act (EU-CRA) Compliance with TI’s Jacinto and Sitara Processors PDF | HTML 24 Apr 2026
Application note GUI Development on AM6x Processors PDF | HTML 25 Mär 2026
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 12 Feb 2026
Application note Linux Audio on Sitara Socs PDF | HTML 12 Dez 2025
Functional safety information AM62x TÜV SÜD Functional Safety Certificate 01 Dez 2025
Application note Getting Started with Sysconfig Tool PDF | HTML 21 Nov 2025
Application note AM62x Audio Design Guide PDF | HTML 20 Nov 2025
User guide Hardware Design Considerations for Custom Board Using AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor (Rev. E) PDF | HTML 24 Okt 2025
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 17 Okt 2025
User guide AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I) PDF | HTML 17 Sep 2025
User guide AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor Family Schematic, Design Guidelines and Review Checklist (Rev. B) PDF | HTML 16 Sep 2025
Application note AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking PDF | HTML 08 Sep 2025
Application note Powering the AM62x with the TPS65219 PMIC (Rev. C) PDF | HTML 18 Aug 2025
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 17 Jul 2025
Application note AM62x, AM62Lx DDR Board Design and Layout Guidelines (Rev. C) PDF | HTML 05 Mär 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 Feb 2025
Application note MCAN Debug Guide PDF | HTML 18 Feb 2025
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 28 Jan 2025
Application note Basic Ethernet Interface Debug With Linux PDF | HTML 11 Okt 2024
Application note Minimal Platform Development on AM62x Devices (Rev. A) PDF | HTML 24 Sep 2024
Functional safety information AM62, AM62A AUTOSAR MCAL Drivers Functional Safety Certificate 16 Aug 2024
Application note AM62x Power Consumption PDF | HTML 16 Feb 2024
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
Application brief Keyword Spotting Using AI at the Edge With Sitara Processors PDF | HTML 28 Sep 2023
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 31 Jul 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note AM62x (AMC) PCB Escape Routing PDF | HTML 22 Sep 2022
Application note AM62x Extended Power-On Hours PDF | HTML 13 Mai 2022
Application note AM62x Power Estimation Tool PDF | HTML 08 Apr 2022

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Debug-Tastkopf

LB-3P-TRACE32-ARM — Debug- und Trace-System Lauterbach TRACE32® für Arm®-basierte Mikrocontroller und Prozessoren

Die TRACE32®-Tools von Lauterbach sind eine Suite hochmoderner Hardware- und Softwarekomponenten, mit denen Entwickler alle Arten von Arm®-basierten Mikrocontrollern und Prozessoren analysieren, optimieren und zertifizieren können. Die weltweit anerkannten Debugging- und Trace-Lösungen für (...)

Von: Lauterbach GmbH
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Software-Entwicklungskit (SDK)

MCU-PLUS-SDK-AM62X — MCU+ SDK for AM62x – RTOS, No-RTOS

The AM62 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-ANDROID-AM62X — Processor SDK Android for AM62x

The AM62 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AM62X — Processor SDK Linux for AM62x

The AM62 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-AM62X — Processor SDK RT-Linux for AM62x

The AM62 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

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Anwendungssoftware und Frameworks

AM62Q-17X17-RESTRICTED-DOCS-SAFETY — AM62x-Q1 functional safety documents

AM62x-Q1 Safety Manual and FMEDA
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Anwendungssoftware und Frameworks

AM62X-RESTRICTED-DOCS-SAFETY — AM62X safety content

AM62X safety content
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Anwendungssoftware und Frameworks

EB-3P-TRESOS — Elektrobit EB tresos Classic AUTOSAR-Software

Mit jahrzehntelanger Erfahrung auf dem Gebiet der Basissoftware trägt Elektrobit mit seiner EB tresos Produktlinie und den maßgeschneiderten Classic AUTOSAR-Lösungen dazu bei, die spezifischen Anforderungen jedes Automobilherstellers zu erfüllen und modernste Software zu liefern. Elektrobit bietet (...)
Von: Elektrobit
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Firmware

DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin

The DDR margin firmware and supporting scripts allow visualization and measurement of system margin in the DDR interface on board. These tools enable probe-less measurement of critical data signals to understand the integrity and robustness of the interface.
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Erste Schritte

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE, Konfiguration, Compiler oder Debugger

CLOCKTREE-AM62X — Clock tree configuration for AM62x


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)

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IDE, Konfiguration, Compiler oder Debugger

DDR-CONFIG-AM62 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE, Konfiguration, Compiler oder Debugger

EDGE-AI-STUDIO — Edge AI Studio

Edge AI Studio is part of the CCStudio™ development tool ecosystem.  Edge AI Studio is a collection of graphical and command line tools designed to accelerate edge AI development on TI processors, microcontrollers, connectivity devices and radar sensors.  It supports both AI-accelerated (...)

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IDE, Konfiguration, Compiler oder Debugger

K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
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SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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Onlineschulungen

AM62-ACADEMY — AM62x Academy

AM62x Academy is designed to simplify and accelerate custom AM62x development.
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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
Von: Green Hills Software
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Betriebssystem (BS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Vorzertifiziertes Sicherheits-RTOS

SAFERTOS® ist ein einzigartiges Echtzeitbetriebssystem für Embedded-Prozessoren. Er ist vom TÜV SÜD nach den Normen IEC 61508 SIL3 und ISO 26262 ASILD vorzertifiziert. SAFERTOS® wurde vom Expertenteam von WHIS speziell auf Sicherheit ausgelegt und wird weltweit in sicherheitskritischen Anwendungen (...)
Von: WITTENSTEIN High Integrity Systems
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Support-Software

RIGHTWARE-3P-KANZI — Rightware Kanzi HMI-Entwicklungssoftwaretool für AM62x-Sitara-Prozessoren

Kanzi is the automotive specialized HMI toolchain that delivers advanced HMI experiences. It achieves an outstanding performance-to-effects ratio on embedded hardware like the AM62P series through effective mapping of its rendering pipeline and resource management to the hardware’s (...)
Von: Rightware
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Support-Software

VCTR-3P-MICROSAR — Vector MICROSAR AUTOSAR-Software für Mikrocontroller und Hochleistungscomputer (HPCs)

Die MICROSAR- und DaVinci-Produktfamilien vereinfachen die Steuergeräte-Entwicklung mit ausgefeilter Embedded-Software und leistungsstarken Entwicklungswerkzeugen für Mikrocontroller und HPCs. Mit fortschrittlicher Infrastruktursoftware schaffen Sie eine optimale Basis für Ihre Steuergeräte und (...)
Von: Vector Informatik GmbH
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Simulationsmodell

AM620-Q1 IBIS model

SPRM886.ZIP (1969 KB) - IBIS Model
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Simulationsmodell

AM62x AMC BSDL Model

SPRM807.ZIP (10 KB) - BSDL Model
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Simulationsmodell

AM62x AMC IBIS Model

SPRM806.ZIP (1970 KB) - IBIS Model
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Simulationsmodell

AM62x AMC Thermal Model

SPRM809.ZIP (1 KB) - Thermal Model
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Berechnungstool

AM62X-PET-CALC — AM62x Power Estimation Tool

The AM62x power-estimation tool (PET) spreadsheet allows the user to calculate power consumption estimates based on measured and simulated data. Estimates are provided as is and are not ensured within a specified precision. Power consumption depends on electrical parameters, silicon process (...)

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCBGA (AMC) 441 Ultra Librarian
FCCSP (ALW) 425 Ultra Librarian
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