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SN74AUP1G74

AKTIV

Energieeffizienter Einzelflipflop (Typ D) mit positiver Flankensteuerung

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Datenblatt

SN74AUP1G74

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 160 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 160 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
DSBGA (YFP) 8 1.8 mm² 1 x 1.8 DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 UQFN (RSE) 8 2.25 mm² 1.5 x 1.5 VSSOP (DCU) 8 6.2 mm² 2 x 3.1 X2SON (DQE) 8 1.4 mm² 1.4 x 1
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption: ICC = 0.9 μA Maximum
  • Low Dynamic-Power Consumption: Cpd = 5.5 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise – Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

    • NanoStar Is a trademark of Texas Instruments. All other trademarks are the property of their respective owners

  • APPLICATIONS
    • Servers
    • LED Displays
    • Network Switches
    • Telecom Infrastructure
    • Motor Drivers
    • I/O Expanders
    •
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption: ICC = 0.9 μA Maximum
  • Low Dynamic-Power Consumption: Cpd = 5.5 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise – Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

    • NanoStar Is a trademark of Texas Instruments. All other trademarks are the property of their respective owners

  • APPLICATIONS
    • Servers
    • LED Displays
    • Network Switches
    • Telecom Infrastructure
    • Motor Drivers
    • I/O Expanders
    •

    The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in ).

    The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in ).
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    Technische Dokumentation

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    Typ Titel Datum
    * Data sheet SN74AUP1G74 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. D) PDF | HTML 29 Dez 2015
    Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dez 2022
    Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 Mai 2019
    Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
    Selection guide Logic Guide (Rev. AB) 12 Jun 2017
    Application note How to Select Little Logic (Rev. A) 26 Jul 2016
    Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

    Design und Entwicklung

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    Gehäuse Pins Herunterladen
    DSBGA (YFP) 8 Optionen anzeigen
    DSBGA (YZP) 8 Optionen anzeigen
    UQFN (RSE) 8 Optionen anzeigen
    VSSOP (DCU) 8 Optionen anzeigen
    X2SON (DQE) 8 Optionen anzeigen
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