Produktdetails

Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 ON-state leakage current (max) (µA) 5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Precharged signal path, Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 ON-state leakage current (max) (µA) 5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Precharged signal path, Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
SSOP (DBQ) 24 51.9 mm² 8.65 x 6 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Power Off Disables Outputs, Permitting Live Insertion
  • Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion
  • Active-Clamp Undershoot-Protection Circuit on the I/Os Clamps Undershoots Down to \x962 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Power Off Disables Outputs, Permitting Live Insertion
  • Outputs Are Precharged by Bias Voltage to Minimize Signal Distortion During Live Insertion
  • Active-Clamp Undershoot-Protection Circuit on the I/Os Clamps Undershoots Down to \x962 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74CBTK6800 device provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the active-clamp circuit is enabled and current from VCC is supplied to clamp the output, preventing the pass transistor from turning on.

The SN74CBTK6800 is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open. When ON\ is high or VCC is 0 V, B port is precharged to BIASV through the equivalent of a 10-k resistor.

The SN74CBTK6800 device provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the active-clamp circuit is enabled and current from VCC is supplied to clamp the output, preventing the pass transistor from turning on.

The SN74CBTK6800 is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open. When ON\ is high or VCC is 0 V, B port is precharged to BIASV through the equivalent of a 10-k resistor.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 10-Bit FET Bus Switch W/ Precharged Outputs and Active-Clamp Undershoot-Prot.Ckt datasheet (Rev. B) 20 Okt 2000
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dez 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06 Jan 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature CBT RAID Application Clip 12 Jun 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 Mai 2002
Application note Flexible Voltage-Level Translation With CBT Family Devices 20 Jul 1999
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dez 1998
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) 03 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dez 1997
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) 01 Mär 1997
Application note Understanding Advanced Bus-Interface Products Design Guide 01 Mai 1996

Design und Entwicklung

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The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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SSOP (DBQ) 24 Ultra Librarian
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