SN74CBTLV3126-Q1

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Produktdetails

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 7 CON (typ) (pF) 2.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 7 CON (typ) (pF) 2.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Standard 126-type pinout
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Standard 126-type pinout
  • 5-Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74CBTLV3126-Q1 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The SN74CBTLV3126-Q1 device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3126-Q1 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The SN74CBTLV3126-Q1 device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Typ Titel Datum
* Data sheet SN74CBTLV3126-Q1 Low-Voltage Quadruple FET Bus Switch datasheet PDF | HTML 11 Dez 2025
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Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
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More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dez 1998
Selection guide Logic Guide (Rev. AC) PDF | HTML 01 Jun 1994

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