SN74LVC16T245

AKTIV

16-Bit-Doppel-Supply-Bustransceiver mit konfigurierbarer Pegel-/Spannungsumsetzung

Produktdetails

Bits (#) 16 Data rate (max) (Mbps) 200 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 4.3 Technology family LVC Supply current (max) (mA) 0.03 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 16 Data rate (max) (Mbps) 200 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 4.3 Technology family LVC Supply current (max) (mA) 0.03 Rating Catalog Operating temperature range (°C) -40 to 85
TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Control Inputs VIH/VIL Levels are Referenced to
    VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at
    GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow
    Mixed Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.65-V to 5.5-V
    Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • Control Inputs VIH/VIL Levels are Referenced to
    VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at
    GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow
    Mixed Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.65-V to 5.5-V
    Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74LVC16T245 16-bit Dual-Supply Bus Transceiver With Configurable Level-Shifting / Voltage Translation and Tri-State Outputs datasheet (Rev. B) PDF | HTML 28.04.2015
Anwendungshinweis Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02.10.2024
Anwendungshinweis Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12.07.2024
Anwendungshinweis Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03.07.2024
Auswahlhilfe Voltage Translation Buying Guide (Rev. A) 15.04.2021

Design und Entwicklung

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Simulationsmodell

SN74LVC16T245 IBIS Model

SCEM492.ZIP (56 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TVSOP (DGV) 48 Ultra Librarian
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

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