GUI para el módulo de evaluación (EVM)
DAC39J84
Convertidor digital a analógico (DAC) de 4 canales, 16 bits, 2,8 GSPS, 1x-16x de interpolación
Hoja de datos
DAC39J84
- Resolution: 16-Bit
- Maximum Sample Rate: 2.8GSPS
- Maximum Input Data Rate: 1.25GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC Synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x –16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Multi-Band Mode: Digital Summation of Independent
Complex Signals - 3/4-Wire Serial Control Bus (SPI)
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Pin-Compatible with Quad-Channel DAC37J84/
DAC38J84 Family - Power Dissipation: 1.8W at 2.8GSPS
- Package: 10 mm × 10 mm, 144-Ball Flip-Chip BGA
The DAC39J84 is a low power, 16-bit, quad-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
Documentación técnica
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Ver todo 4 | Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet (Rev. A) | PDF | HTML | 26 ene 2015 |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 27 sep 2017 | ||
| EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 28 abr 2016 | ||
| Application note | System solution for avionics & defense | 23 sep 2015 |
Diseño y desarrollo
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
Placa de evaluación
DAC39J84EVM — Convertidor digital a analógico DAC39J84 EVM de cuatro canales, 16 bits, 2,8 GSPS, 1x-16x con interp
The DAC39J84EVM is an evaluation module (EVM) designed to evaluate the DAC39J84 high-speed, JESD204B interface DAC. The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.
The DAC39J84EVM is designed (...)
Guía del usuario: PDF
Placa de evaluación
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Desde: Abaco Systems
Firmware
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The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Herramienta de simulación
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Diseños de referencia
TIDA-00996 — Diseño de referencia de transmisor múltiple sincronizado: Método de alineación temporal de varias DA
To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
Diseños de referencia
TIDA-00335 — Diseño de referencia de transmisor de alta frecuencia y alto ancho de banda
This design illustrates the circuit modifications required to support high bandwidth and high frequency applications using current source DACs like the DAC38J84 with the TRF3704 modulator. The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths. The (...)
| Paquete | Pasadores | Descargar |
|---|---|---|
| FCCSP (AAV) | 144 | Ver opciones |
Pedidos y calidad
Información incluida:
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
Información incluida:
- Lugar de fabricación
- Lugar de ensamblaje
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Soporte y capacitación
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