SN74AUC2G241

ACTIVO

Búferes de alta velocidad, de 2 canales, 0.8 V a 2.7 V con salidas de 3 estados

Detalles del producto

Technology family AUC Number of channels 2 IOL (max) (mA) 9 Supply current (max) (µA) 10 IOH (max) (mA) -9 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUC Number of channels 2 IOL (max) (mA) 9 Supply current (max) (µA) 10 IOH (max) (mA) -9 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm)
  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.9 ns at 1.8 V
  • Low Power Consumption, 10 µA at 1.8 V
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.9 ns at 1.8 V
  • Low Power Consumption, 10 µA at 1.8 V
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC2G241 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC2G241 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

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Documentación técnica

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* Hoja de datos SN74AUC2G241 datasheet (Rev. C) 12/01/2007

Diseño y desarrollo

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Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación de lógico genérico para encapsulados DCK, DCT, DCU, DRL y DBV,de 5- a 8-pines

EVM flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV y entre 5 y 8 pines.
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Modelo de simulación

SN74AUC2G241 Behavioral SPICE Model

SCEM707.ZIP (7 KB) - Modelo PSpice
Productos y hardware compatibles
Modelo de simulación

SN74AUC2G241 IBIS Model (Rev. A)

SCEM391 (432 KB) - Modelo IBIS
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
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VSSOP (DCU) 8 Ultra Librarian

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