LM25115
- Self-synchronization to Main Channel Output
- Free-run Mode for Buck Regulation of DC Input
- Leading Edge Pulse Width Modulation
- Voltage-mode Control with Current Injection and Input Line Feed-forward
- Operates from AC or DC Input up to 42V
- Wide 4.5V to 30V Bias Supply Range
- Wide 0.75V to 13.5V Output Range.
- Top and Bottom Gate Drivers Sink 2.5A Peak
- Adaptive Gate Driver Dead-time Control
- Wide Bandwidth Error Amplifier (4MHz)
- Programmable Soft-start
- Thermal Shutdown Protection
- TSSOP-16 or Thermally Enhanced WSON-16 Packages
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The LM25115 controller contains all of the features necessary to implement multiple output power converters utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM25115 drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | LM25115 Secondary Side Post Regulator Controller データシート (Rev. A) | 2013/04/01 | |||
| ホワイト・ペーパー | Valuing wide VIN, low EMI synchronous buck circuits for cost-driven, demanding a (Rev. A) | 2019/04/10 | ||||
| セレクション・ガイド | 電源 IC セレクション・ガイド 2018 (Rev. R 翻訳版) | 英語版 (Rev.R) | 2018/09/13 | |||
| アナログ デザイン ジャーナル | Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics | 2016/07/21 | ||||
| アプリケーション・ノート | Minimizing FET Losses For a High Input Rail Buck Converter (Rev. A) | 2013/04/23 |
設計と開発
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LM25115 Unencrypted PSpice Transient Model Package (Rev. A)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| WSON (NHQ) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |