ホーム パワー・マネージメント AC/DC & DC/DC controllers (external FET)

UCC2583

アクティブ

-40℃ ~ 85℃、スイッチ・モード、2 次側ポスト・レギュレータ

製品詳細

Vin (max) (V) 15 Operating temperature range (°C) -40 to 85 Control mode Current Topology Secondary side regulator Rating Catalog Duty cycle (max) (%) 95
Vin (max) (V) 15 Operating temperature range (°C) -40 to 85 Control mode Current Topology Secondary side regulator Rating Catalog Duty cycle (max) (%) 95
PLCC (FN) 20 98.01 mm² 9.9 x 9.9 SOIC (D) 14 51.9 mm² 8.65 x 6
  • Precision Secondary Side Post Regulation for Multiple Output Power Supplies
  • Useful for Both Single Ended and Center Tapped Secondary Circuits
  • Ideal Replacement for Complex Magnetic Amplifier Regulated Circuits
  • Leading Edge Modulation
  • Does Not Require Gate Drive Transformer
  • High Frequency (>500kHz) Operation
  • Applicable for Wide Range of Output Voltages
  • High Current Gate Driver (0.5A Sink/1.5A Source)
  • Average Current Limiting Loop

  • Precision Secondary Side Post Regulation for Multiple Output Power Supplies
  • Useful for Both Single Ended and Center Tapped Secondary Circuits
  • Ideal Replacement for Complex Magnetic Amplifier Regulated Circuits
  • Leading Edge Modulation
  • Does Not Require Gate Drive Transformer
  • High Frequency (>500kHz) Operation
  • Applicable for Wide Range of Output Voltages
  • High Current Gate Driver (0.5A Sink/1.5A Source)
  • Average Current Limiting Loop

The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.

The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.

The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions.

The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.

The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.

The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート Switch Mode Secondary Side Post Regulator データシート (Rev. B) 2005年 1月 18日

設計と開発

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パッケージ ピン数 ダウンロード
PLCC (FN) 20 オプションの表示
SOIC (D) 14 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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