홈 데이터 컨버터 아날로그-디지털 컨버터(ADC) 고속 ADC(≥10 MSPS)
홈
데이터 컨버터
아날로그-디지털 컨버터(ADC)
고속 ADC(≥10 MSPS)

ADC12DJ3200QML-SP

활성

Radiation-hardened, QML-V, 300krad, 12 bit, dual 3.2GSPS or single 6.4GSPS ADC

지금 주문하기
데이터 시트

ADC12DJ3200QML-SP

활성
데이터 시트 지금 주문하기

제품 상세 정보

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² (15 mm × 15 mm)
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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기술 자료

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10개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) PDF | HTML 2025. 3. 21
* 방사능 및 안정성 보고서 ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 2020. 8. 3
* 방사능 및 안정성 보고서 Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012. 5. 4
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 2020. 8. 4
선택 가이드 TI Space Products (Rev. L) 2026. 3. 27
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025. 6. 17
애플리케이션 노트 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025. 6. 10
추가 자료 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025. 2. 20
애플리케이션 노트 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022. 10. 19
기술 문서 How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 2022. 10. 17

설계 및 개발

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평가 보드

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 평가 모듈

ADC12DJ3200 EVM(평가 모듈)은 ADC12DJ3200QML-SP 고속 ADC(아날로그-디지털 컨버터)를 평가하도록 설계되었습니다. EVM에는 JESD204B 인터페이스를 지원하는 항공우주 등급 12비트, 듀얼 채널 4GSPS 또는 싱글 채널 8GSPS ADC인 ADC12DJ3200QML-SP가 장착되어 있습니다.
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JESD204 고속 설계 IP는 TI 고속 데이터 컨버터와 함께 사용할 수 있도록 로열티 없이 제공됩니다. TI는 특정 FPGA 플랫폼과 TI 데이터 (...)

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SLVC806 — Xilinx AlphaData Demo

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ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

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ADC12DJ3200QML-SP S-Parameter Model

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