ADS6445-EP

활성

쿼드 채널, 14비트, 125MSPS 아날로그-디지털 컨버터(ADC) - EP(Enhanced Product)

제품 상세 정보

Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1680 Architecture Pipeline SNR (dB) 73.7 ENOB (Bits) 11.7 SFDR (dB) 87 Operating temperature range (°C) -55 to 125 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1680 Architecture Pipeline SNR (dB) 73.7 ENOB (Bits) 11.7 SFDR (dB) 87 Operating temperature range (°C) -55 to 125 Input buffer No
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5-dB Coarse Gain and up to 6-dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs and Amplitude Down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64-pin QFN Package (9 mm × 9 mm)
  • Feature Compatible Dual Channel Family
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5-dB Coarse Gain and up to 6-dB Programmable
    Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable
    Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs and Amplitude Down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64-pin QFN Package (9 mm × 9 mm)
  • Feature Compatible Dual Channel Family

The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.

The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified over –55°C to 125°C operating junction temperature range.

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기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
8개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS datasheet (Rev. C) 2013. 5. 29
* 방사능 및 안정성 보고서 ADS6445MRGCTEP Reliability Report 2014. 12. 22
애플리케이션 노트 Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010. 9. 10
애플리케이션 노트 Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009. 4. 28
애플리케이션 노트 CDCE62005 as Clock Solution for High-Speed ADCs 2008. 9. 4
애플리케이션 노트 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008. 6. 8
애플리케이션 노트 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008. 6. 2
애플리케이션 노트 QFN Layout Guidelines 2006. 7. 28

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

지원 소프트웨어

HSADC-SPI-UTILITY — ADS5400 EVM GUI

지원되는 제품 및 하드웨어
계산 툴

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

아날로그 엔지니어의 계산기는 아날로그 회로 설계 엔지니어가 정기적으로 사용하는 많은 반복 계산의 속도를 높이도록 설계되었습니다. 이 PC 기반 툴은 피드백 저항을 사용한 연산 증폭기 게인 설정부터 아날로그-디지털 컨버터(ADC) 드라이브 버퍼 회로 안정화를 위한 적절한 회로 설계 요소 선택에 이르기까지 다양한 일반적인 계산 목록이 포함된 그래픽 인터페이스를 제공합니다.

이 계산기는 독립 실행형 툴로 유용할 뿐만 아니라 아날로그 엔지니어의 포켓 레퍼런스에 설명된 개념과도 잘 어울립니다.

지원되는 제품 및 하드웨어
패키지 CAD 기호, 풋프린트 및 3D 모델
VQFN (RGC) 64 Ultra Librarian

주문 및 품질

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

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