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AFE79XX-HSC-DESIGN — AFE79xx family high-speed transceiver design & support files
Find detailed product information on the AFE79xx product family (datasheets, EVM resources, software and firmware, reference designs, etc)
데이터 시트
AFE7906
- Request full data sheet
- Six RF sampling 14 bit, 3GSPS ADCs
- Maximum RF signal bandwidth:
- 4 ADCs: 1200MHz per ADC
- 6 ADCs: 600MHz per ADC
- RF frequency range: 5MHz - 12GHz
- Digital step attenuators (DSA): 25dB range, 0.5dB steps
- Single DDC (on 6 channels) or dual-band DDCs (on 4 channels)
- 16x NCOs per DDC channel
- Optional Internal PLL/VCO for ADC clocks or external clock at ADC sample rate
- Sysref alignment detector
- SerDes data interface:
- JESD204B and JESD204C compatible
- 8 SerDes transmitters up to 29.5Gbps
- Subclass 1 multi-device synchronization
- Package: 17mm × 17mm FCBGA, 0.8mm pitch
The AFE7906 is a high performance, wide bandwidth multi-channel receiver, integrating six RF Sampling ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Four receiver channels have an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX or 600MHz.
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
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7개 모두 보기 | 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | AFE7906 6-Channel, 5MHz to 12GHz RF Sampling Receiver with 3GSPS ADCs datasheet (Rev. D) | PDF | HTML | 2025/05/02 |
| Application note | AFE79xx Bringup Using HDL Module Without Microcontroller | PDF | HTML | 2025/08/14 | |
| Application note | Debugging AFE7950 for Run Time and Post Bring-Up Failure | PDF | HTML | 2024/06/28 | |
| User guide | AFE79xx SPI Bringup Guide With Xilinx FPGAs (Rev. A) | PDF | HTML | 2024/05/05 | |
| Application note | Determining Optimal Receive Buffer Delay in JESD204B and JESD204C Receivers | PDF | HTML | 2022/07/07 | |
| Application note | AFE7950 Super-Heterodyne Solution for K-Band | PDF | HTML | 2022/02/15 | |
| Application note | How to Achieve Frequency Hopping with the AFE79xx | 2020/07/02 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
평가 보드
AFE7900EVM — AFE7900 4전송, 6수신, 5MHz~7400MHz RF 샘플링 AFE용 평가 모듈
AFE7900 제품군 평가 모듈(EVM)은 최대 4개의 전송, 4개의 수신 및 2개의 피드백(4T4R+2FB) 채널을 동시에 지원하도록 구성할 수 있는 RF 샘플링 송수신기 플랫폼입니다. EVM는 아래 TI 패턴/캡처 카드 솔루션(별도 판매)뿐만 아니라 많은 FPGA FMC 호환 개발 키트와 상호 작용합니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
| FCBGA (ALK) | 400 | Ultra Librarian |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.