제품 상세 정보

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 15 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 15 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6
  • Wide Analog-Input-Voltage Range . . . . 0V - 10V
  • Low "ON" Resistance
    • VCC = 4.5V . . . . . . . .25
    • VCC = 9V . . . . . . . .15
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V and 10V
  • HCT Types
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

  • Wide Analog-Input-Voltage Range . . . . 0V - 10V
  • Low "ON" Resistance
    • VCC = 4.5V . . . . . . . .25
    • VCC = 9V . . . . . . . .15
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V and 10V
  • HCT Types
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

The ’HC4066 and CD74HCT4066 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear "ON" resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input.

The ’HC4066 and CD74HCT4066 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear "ON" resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input.

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기술 문서

star =TI에서 선정한 이 제품의 인기 문서
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모두 보기14
유형 직함 날짜
* Data sheet CD54HC4066, CD74HC4066, CD74HCT4066 datasheet (Rev. D) 2003/08/21
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/06/02
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/01
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
패키지 다운로드
PDIP (N) 14 옵션 보기
SOIC (D) 14 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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