패키징 정보
| 패키지 | 핀 DSBGA (YFP) | 8 |
| 작동 온도 범위(°C) -40 to 85 |
| 패키지 수량 | 캐리어 3,000 | LARGE T&R |
CDC3RL02의 주요 특징
- Low Additive Noise:
- –149dBc/Hz at 10kHz Offset Phase Noise
- 0.37ps (RMS) Output Jitter
- Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads)
- Adaptive Output Stage Controls Reflection
- Regulated 1.8V Externally Available I/O Supply
- Ultra-Small 8-bump YFP 0.4mm Pitch WCSP (0.8mm × 1.6mm)
- ESD Performance Exceeds JESD 22
- 2000V Human-Body Model (A114-A)
- 1000V Charged-Device Model (JESD22-C101-A Level III)
CDC3RL02에 대한 설명
The CDC3RL02 is a two-channel clock fan-out buffer and is designed for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. The device buffers a single clock source, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each input can enable a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3V signal (peak-to-peak). CDC3RL02 is designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines.
The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3V to 5.5V and outputs 1.8V, 50mA. This 1.8V supply is externally available to provide regulated power to peripheral devices such as a TCXO.
The CDC3RL02 is offered in a 0.4mm pitch die size ball grid array (DSBGA) package (0.8mm × 1.6mm), also known as wafer-level chip-scale (WCSP) package, and is optimized for very low standby current consumption.