제품 상세 정보

Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 533 Number of outputs 1 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 0 Features Rambus XDR Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type CMOS
Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 533 Number of outputs 1 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 0 Features Rambus XDR Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type CMOS
SSOP (DBQ) 24 51.9 mm² 8.65 x 6
  • 533-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 1066-MHz Data Transfer Rate
  • Fail-Safe Power Up Initialization
  • Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock
  • Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications
  • Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ)
  • Packaged in a Shrink Small-Outline Package (DBQ)
  • Supports Frequency Multipliers: 4, 6, 8, 16/3
  • No External Components Required for PLL
  • Supports Independent Channel Clocking
  • Spread Spectrum Clocking Tracking Capability to Reduce EMI
  • Designed for Use With TI’s 133-MHz Clock Synthesizers CDC924 and CDC921
  • Cycle-Cycle Jitter Is Less Than 40 ps at 533 MHz
  • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement
  • Supports Industrial Temperature Range of –40°C to 85°C

DIRECT RAMBUS, Rambus are trademarks of Rambus Inc.

  • 533-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 1066-MHz Data Transfer Rate
  • Fail-Safe Power Up Initialization
  • Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock
  • Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications
  • Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ)
  • Packaged in a Shrink Small-Outline Package (DBQ)
  • Supports Frequency Multipliers: 4, 6, 8, 16/3
  • No External Components Required for PLL
  • Supports Independent Channel Clocking
  • Spread Spectrum Clocking Tracking Capability to Reduce EMI
  • Designed for Use With TI’s 133-MHz Clock Synthesizers CDC924 and CDC921
  • Cycle-Cycle Jitter Is Less Than 40 ps at 533 MHz
  • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement
  • Supports Industrial Temperature Range of –40°C to 85°C

DIRECT RAMBUS, Rambus are trademarks of Rambus Inc.

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing.

The CDCFR83A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.

The CDCFR83A is characterized for operation over free-air temperatures of –40°C to 85°C.

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing.

The CDCFR83A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.

The CDCFR83A is characterized for operation over free-air temperatures of –40°C to 85°C.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
1개 모두 보기
유형 직함 날짜
* Data sheet Direct Rambus(TM) Clock Generator datasheet 2005/08/25

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

CDCFR83A IBIS Model

SCAC069.ZIP (12 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DBQ) 24 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상