DS110DF1610
- Pin-Compatible Family
- DS150DF1610: 12.5 - 15G
- DS125DF1610: 9.8 to 12.5G
- DS110DF1610: 8.5 – 11.3G
- 4x4 Analog Cross Point Switch for Each Quad
- Fully-Adaptive CTLE
- Self-Tuning DFE, With Optional Continuous Adaption
- On-Chip, AC-coupling on Receive Inputs
- Adjustable Transmit VOD
- Adjustable 3-Tap Transmit FIR Filter
- Locks to Half/Quarter/Eighth Data Rates For Legacy Support
- On-Chip Eye Monitor (EOM), PRBS Checker, PRBS Pattern Generator
- Supports IEEE 1149.1 and 1149.6
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection
- Single 2.5-V ±5% Power Supply
- SMBus-Based Register Configuration
- Optional EEPROM Configuration
- 15-mm × 15-mm, 196-Pin FCBGA Package
- Operating Temp Range : –10°C to +85°C
The DS110DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning. The device includes a full adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS110DF1610 independently locks to serial data at 8.5 to 11.3 Gbps and any supported sub-multiple. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream can be used as a reference clock to speed up the lock process. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS110DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS110DF1610 8.5- to 11.3-Gbps 16-Channel Retimer datasheet (Rev. A) | PDF | HTML | 2017/06/15 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023/01/31 | ||
| Analog Design Journal | Green box testing: A method for optimizing high-speed serial links | 2016/07/21 | ||
| Application note | Understanding EEPROM Programming for 10G to 12.5G Retimers | 2016/01/13 |
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCBGA (ABB) | 196 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치