SN54LS195A

활성

4비트 병렬 액세스 시프트 레지스터

제품 상세 정보

Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • Parallel Inputs and Outputs from Each Flip-Flop
  • Direct Overriding Clear
  • J and K\ Inputs to First Stage
  • Complementary Outputs from Last Stage
  • For Use in High Performance:
    • Accumulators/Processors
    • Serial-to-Parallel, Parallel-to-Serial Converters

 

  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • Parallel Inputs and Outputs from Each Flip-Flop
  • Direct Overriding Clear
  • J and K\ Inputs to First Stage
  • Complementary Outputs from Last Stage
  • For Use in High Performance:
    • Accumulators/Processors
    • Serial-to-Parallel, Parallel-to-Serial Converters

 

These 4-bit registers feature parallel inputs, parallel outputs, J-K\ serial inputs, shift/load (SH/LD\) control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The register has two modes of operation:

Parallel (broadside) loadShift (in the direction QA toward QD)

Parallel loading is accomplished by applying the four bits of data and taking SH/LD\ low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when SH/LD\ is high. Serial data for this mode is entered at the J-K\ inputs. These inputs permit the first stage to perform as a J-K\, D-, or T-type flip-flop as shown in the function table.

The high-performance 'S195, with a 105-megahertz typical maximum shift-frequency, is particularly attractive for very-high-speed data processing systems. In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register.

 

These 4-bit registers feature parallel inputs, parallel outputs, J-K\ serial inputs, shift/load (SH/LD\) control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The register has two modes of operation:

Parallel (broadside) loadShift (in the direction QA toward QD)

Parallel loading is accomplished by applying the four bits of data and taking SH/LD\ low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when SH/LD\ is high. Serial data for this mode is entered at the J-K\ inputs. These inputs permit the first stage to perform as a J-K\, D-, or T-type flip-flop as shown in the function table.

The high-performance 'S195, with a 105-megahertz typical maximum shift-frequency, is particularly attractive for very-high-speed data processing systems. In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register.

 

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기술 자료

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11개 모두 보기
유형 직함 날짜
* Data sheet 4-Bit Parallel-Access Shift Registers datasheet 1988/03/01
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Designing with the SN54/74LS123 (Rev. A) 1997/03/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01

설계 및 개발

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패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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