SN74AUP2G04
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption:
ICC = 0.9 µA Max - Low Dynamic-Power Consumption:
Cpd = 4.3 pF Typ at 3.3 V - Low Input Capacitance: Ci = 1.5 pF Typ
- Low Noise: Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.3 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
NanoStar is a trademark of Texas Instruments
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 1).
The SN74AUP2G04 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN74AUP2G04 Low-Power Dual Inverter Gate datasheet (Rev. B) | 2010/03/31 | |
Application brief | Understanding Schmitt Triggers (Rev. A) | PDF | HTML | 2019/05/22 | |
Selection guide | Little Logic Guide 2018 (Rev. G) | 2018/07/06 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | How to Select Little Logic (Rev. A) | 2016/07/26 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
DSBGA (YFP) | 6 | Ultra Librarian |
SOT-SC70 (DCK) | 6 | Ultra Librarian |
USON (DRY) | 6 | Ultra Librarian |
X2SON (DSF) | 6 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치