SN74AUP2G07

Name: SN74AUP2G07
Brand: TI
SKU: SN74AUP2G07
Price: 0.06 USD

활성

오픈 드레인 출력을 지원하는 2채널, 0.8V~3.6V 저전력 버퍼

지금 주문

데이터 시트

document-pdfAcrobat SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E) (영어) PDF | HTML

SN74AUP2G07

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

0.9

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

0.9

IOH (max) (mA)

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YFP)

1.4000000000000001 mm² 1 x 1.4000000000000001

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

USON (DRY)

1.45 mm² 1.45 x 1

X2SON (DSF)

1 mm² 1 x 1

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

filter

기타 비인버팅 버퍼 및 드라이버 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

SN74LVC2G07

활성

오픈 드레인 출력을 지원하는 2채널, 1.65V~5.5V 버퍼 Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)

기술 자료

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6개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E)	PDF \| HTML	2021/10/04
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	2019/05/22
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08