SN74F175
- Contains Four Flip-Flops With Double-Rail Outputs
- Buffered Clock and Direct Clear Inputs
- Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
기술 자료
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1개 모두 보기 유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | Quadruple D-Type Flip-Flop With Clear datasheet (Rev. B) | 2002/05/22 |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치