SN74F299

활성

범용 시프트/저장소 레지스터

제품 상세 정보

Configuration Universal Bits (#) 8 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (µA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 8 Technology family F Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 24 IOH (max) (mA) -3 Supply current (max) (µA) 95000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers
  • Four Modes of Operation:
    • Hold (Store)
    • Shift Right
    • Shift Left
    • Load Data
  • Operates With Outputs Enabled or at High Impedance
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • Direct Overriding Clear
  • Applications:
    • Stacked or Push-Down Registers
    • Buffer Storage
    • Accumulator Registers

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs but has no effect on clearing, shifting, or storage of data.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
SN74HCT595 활성 TLL 호환 CMOS 입력 및 3상 출력 레지스터에 대한 8비트 시프트 레지스터 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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10개 모두 보기
유형 직함 날짜
* Data sheet SN54F299, SN74F299 datasheet (Rev. B) 2004/04/16
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
패키지 CAD 기호, 풋프린트 및 3D 모델
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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