홈 로직 및 전압 변환 로직 게이트 OR 게이트
홈
로직 및 전압 변환
로직 게이트
OR 게이트

SN74LVC2G32-Q1

활성

오토모티브, 2채널 2입력 1.65V~5.5V 32mA 드라이브 강도 OR 게이트

지금 주문
데이터 시트

SN74LVC2G32-Q1

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C
      Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Inputs Accept Voltages to 5.5 V
  • Max Propagation (Delay) Time of 3.8 ns at 3.3 V
  • Low Power Consumption, 10-µA Max Supply Current
  • ±24-mA Output Drive at 3.3 V
  • Typical Voltage Output Low Peak (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical Voltage Output High Valley (VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff State Current Supports Partial-Power-Down Mode
    Operation
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C
      Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Inputs Accept Voltages to 5.5 V
  • Max Propagation (Delay) Time of 3.8 ns at 3.3 V
  • Low Power Consumption, 10-µA Max Supply Current
  • ±24-mA Output Drive at 3.3 V
  • Typical Voltage Output Low Peak (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical Voltage Output High Valley (VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff State Current Supports Partial-Power-Down Mode
    Operation

This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.

The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.

The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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기술 자료

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28개 모두 보기
유형 직함 날짜
* Data sheet Dual 2-input Positive OR gate datasheet 2012/08/03
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
More literature Automotive Logic Devices Brochure 2014/08/27
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01
Selection guide Logic Guide (Rev. AC) PDF | HTML 1994/06/01

설계 및 개발

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평가 보드

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사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

SN74LVC2G32 Behavioral SPICE Model

SCEM612.ZIP (7 KB) - PSpice Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
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주문 및 품질

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  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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