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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

66AK2L06

現行

多核心 DSP+ARM KeyStone II 晶片系統 (SoC)

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產品規格表

66AK2L06

現行
產品規格表 立即訂購

產品詳細資料

CPU 32-/64-bit PCIe 2 PCIe Gen2 Hardware accelerators Digital Front End, FFT Coprocessor Features 4 lanes JESD204B Operating system INTEGRITY, Linux, Neutrino, PrOS, Windows Embedded CE Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
CPU 32-/64-bit PCIe 2 PCIe Gen2 Hardware accelerators Digital Front End, FFT Coprocessor Features 4 lanes JESD204B Operating system INTEGRITY, Linux, Neutrino, PrOS, Windows Embedded CE Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CMS) 900 625 mm² (25 mm × 25 mm)
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet 2015/4/21
* 勘誤表 66AK2Lxx Multicore DSP+ARM KeyStone II SOC (Silicon Revision 1.0) 2015/4/20
應用說明 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/7/7
應用說明 Keystone Error Detection and Correction EDC ECC (Rev. A) 2021/6/25
應用說明 Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019/6/4
使用指南 KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017/8/21
應用說明 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/8/14
使用指南 Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/7/26
設計指南 Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 2016/9/23
應用說明 Keystone EDMA FAQ 2016/9/1
Third party document XEVMK2LX Quick Setup Guide 2016/8/3
Third party document Download XEVMK2LX schematics, bill of materials and design guide 2016/8/3
使用指南 Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016/7/27
應用說明 Power Management of KS2 Device (Rev. C) 2016/7/15
應用說明 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 2016/6/20
技術文章 How to complete your RF sampling solution PDF | HTML 2016/5/18
應用說明 SERDES Link Commissioning on KeyStone I and II Devices 2016/4/13
技術文章 Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more PDF | HTML 2016/3/2
白皮書 Multicore SoCs stay a step ahead of SoC FPGAs 2016/2/23
應用說明 TI DSP Benchmarking PDF | HTML 2016/1/13
應用說明 Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015/12/22
白皮書 Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce 2015/12/17
技術文章 Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment? PDF | HTML 2015/12/2
白皮書 Optimizing your test and measurement solution by leveraging the most integrated 2015/11/3
設計指南 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 2015/10/22
應用說明 Keystone II DDR3 Debug Guide 2015/10/16
應用說明 System solution for avionics & defense 2015/9/23
應用說明 TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC Mode 2015/9/18
技術文章 Summertime showdown: DSPs vs FPGAs PDF | HTML 2015/7/9
使用指南 Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 2015/5/6
技術文章 Wireless infrastructure - Now simpler and more accessible! PDF | HTML 2015/5/5
使用指南 Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015/4/28
Product overview 66AK2L06 SoC Product Bulletin 2015/4/15
使用指南 Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/4/9
白皮書 Optimizing synthetic aperture radar design with TI's integrated 66AK2L06 SoC 2015/4/9
使用指南 DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015/3/27
使用指南 Digital Front End (DFE) for Keystone II Devices User's Guide (Rev. A) 2015/3/23
白皮書 Ready to make the jump to JESD204B? White Paper (Rev. B) 2015/3/19
使用指南 Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A) 2015/2/11
應用說明 Keystone II DDR3 Initialization 2015/1/26
使用指南 IQN2 for KeyStone II Devices User's Guide (Rev. A) 2014/10/1
使用指南 Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/9/4
使用指南 Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014/8/19
使用指南 Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014/8/19
使用指南 Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014/8/13
應用說明 Hardware Design Guide for KeyStone II Devices 2014/3/24
使用指南 Debug and Trace for KeyStone II Devices User's Guide 2013/7/26
使用指南 DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013/7/15
使用指南 Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/6/28
使用指南 C66x CorePac User's Guide (Rev. C) 2013/6/28
使用指南 Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012/11/12
使用指南 ARM CorePac User Guide for KeyStone II Devices 2012/10/31
應用說明 Multicore Programming Guide (Rev. B) 2012/8/29
使用指南 Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 2012/4/24
使用指南 Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/3/30
使用指南 Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/3/27
使用指南 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/3/22
應用說明 PCIe Use Cases for KeyStone Devices 2011/12/13
應用說明 Introduction to TMS320C6000 DSP Optimization 2011/10/6
使用指南 Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/9/2
使用指南 External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/5/24
白皮書 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011/5/19
應用說明 Optimizing Loops on the C66x DSP 2010/11/9
使用指南 General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/9
使用指南 C66x CPU and Instruction Set Reference Guide 2010/11/9
應用說明 Clocking Design Guide for KeyStone Devices 2010/11/9
使用指南 C66x DSP Cache User's Guide 2010/11/9

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2L — Linux Processor SDK for K2L

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2L — Linux-RT Processor SDK for K2L

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-K2L — RTOS Processor SDK for K2L

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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軟體開發套件 (SDK)

RFSDK — 射頻軟體開發套件 (RFSDK)

Texas Instruments Radio Frequency Software Development Kit (RFSDK) is a collection of highly optimized APIs and highly abstracted commands to control, configure and manage the JESD204B interface, digital front end (DFE), analog front end (AFE) and high speed data converters (ADC/DAC). The RFSDK (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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軟體轉碼器

C66XCODECS — 轉碼器 - 視訊、語音 - 適用於 C66x 架構產品

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)

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模擬型號

66AK2L06 Power Consumption Model

SPRM656.ZIP (169 KB) - 功率模型
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI 模型
lock = 需要匯出核准 (1 分鐘)
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模擬型號

TCI6630K2L Power Consumption Model

SPRM660.ZIP (167 KB) - 功率模型
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模擬型號

TCI6632K2L TCI6631K2L and TCI6630K2L AAW IBIS Model

SPRM589.ZIP (3192 KB) - IBIS 模型
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參考設計

TIDEP0034 — 連接至寬頻 ADC 和 DAC 且具有 JESD204B 的 66AK2L06 DSP+ARM 處理器

對於目前使用 FPGA 或 ASIC 連接高速資料轉換器的開發人員，因其需要透過提升性能並大幅降低成本、功耗和尺寸來加快上市速度，此參考設計十分適合，因為其中包括首款整合了 JESD204B 介面和數位前端 (DFE) 處理功能的廣泛可用型處理器。連接到 ADC12J4000 和 DAC38J84 後，可為測試和測量及國防應用提供高效解決方案。

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參考設計

TIDEP0060 — 使用 DSP+ARM SoC 的最佳化雷達系統參考設計

對於目前使用 FPGA 或 ASIC 連接高速資料轉換器的現代雷達系統開發人員，因其需要透過提升性能並大幅降低成本、功耗和尺寸來加快上市速度，此參考設計十分適合，因為其中包括首款整合了 JESD204B 介面和數位前端 (DFE) 處理功能的廣泛可用型處理器。連接至 ADC14X250 和 DAC38J84 可為雷達、電子作戰、運算平台和轉發器等航空電子與國防應用提供高效率的解決方案。
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參考設計

TIDEP0081 — 使用 66AK2L06 JESD204B 連接 ADC32RF80 的寬頻接收器參考設計

對於目前使用 FPGA 或 ASIC 將高速資料轉換器連接至基頻處理器的寬頻接收器系統開發人員而言，若需加快上市時程、提升效能並大幅降低成本、功耗與體積，這項參考設計即為理想解決方案。本參考設計包含首款廣泛可用、整合 JESD204B 介面與數位前端處理 (DFE) 的處理器。將 ADC32RF80 連接至 DAC38J84，能為航太與國防、測試與量測以及工業應用提供高效率解決方案。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (CMS) 900 Ultra Librarian
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