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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM5K2E04

現行

Sitara 處理器：四 Arm Cortex-A15

立即訂購
產品規格表

AM5K2E04

現行
產品規格表 立即訂購

產品詳細資料

CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² (27 mm × 27 mm)
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 2015/3/11
* 勘誤表 AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 2015/8/20
使用指南 ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023/3/30
使用指南 ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023/3/30
應用說明 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/7/7
應用說明 Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019/6/4
應用說明 Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019/5/17
應用說明 KeyStone II DDR3 interface bring-up PDF | HTML 2019/3/7
使用指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/9/24
使用指南 KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017/8/21
應用說明 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/8/14
使用指南 Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/7/26
應用說明 Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 2017/6/14
應用說明 Clocking Spreadsheet for K2E Device Family 2017/1/26
使用指南 Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016/7/27
應用說明 Power Management of KS2 Device (Rev. C) 2016/7/15
應用說明 Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015/12/22
應用說明 Keystone II DDR3 Debug Guide 2015/10/16
使用指南 Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 2015/5/6
使用指南 Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015/4/28
使用指南 Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/4/9
使用指南 DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015/3/27
白皮書 Save power and costs with TI's K2E on-chip networking features 2015/3/25
應用說明 Keystone II DDR3 Initialization 2015/1/26
使用指南 Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/9/4
白皮書 KeyStone™-II-based processors: 10G Ethernet as an optical interface 2014/8/25
使用指南 Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014/8/19
使用指南 Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014/8/19
白皮書 Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 2014/8/14
使用指南 Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014/8/13
應用說明 Hardware Design Guide for KeyStone II Devices 2014/3/24
使用指南 PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013/9/30
使用指南 Debug and Trace for KeyStone II Devices User's Guide 2013/7/26
使用指南 ARM Bootloader User Guide for KeyStone II Devices 2013/7/21
使用指南 Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/6/28
使用指南 HyperLink for KeyStone Devices User's Guide (Rev. C) 2013/5/28
使用指南 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 2013/2/8
使用指南 Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012/11/12
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 2012/11/9
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 2012/11/9
使用指南 ARM CorePac User Guide for KeyStone II Devices 2012/10/31
應用說明 Multicore Programming Guide (Rev. B) 2012/8/29
使用指南 Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/3/30
使用指南 Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/3/27
使用指南 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/3/22
應用說明 PCIe Use Cases for KeyStone Devices 2011/12/13
使用指南 Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/9/2
使用指南 External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/5/24
應用說明 Optimizing Loops on the C66x DSP 2010/11/9
使用指南 General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/9
應用說明 Clocking Design Guide for KeyStone Devices 2010/11/9
使用指南 Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010/11/9
使用指南 C66x DSP Cache User's Guide 2010/11/9
使用指南 Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 2010/11/9

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發套件

EVMK2EX — K2E 開發基板

EVMK2EX 是一款功能完整的開發工具 ，適用於基於 KeyStone II 架構的 66AK2Exx 和 AM5K2Exx SoC。使用這款雙寬 AMC 規格評估板，內建單顆 66AK2E05 四核心 ARM Cortex-A15 處理器與 C66x DSP，立即開始開發適用於工業、關鍵任務及網路應用的通用嵌入式運算系統。

此套件隨附完整軟體套件，包括 Code Composer Studio 整合式開發環境第 5 版 (CCS v5)、TI 多核心軟體開發套件 (MCSDK) 具備支援 ARM 核心的 Linux 以及 DSP 核心的 SYS/BIOS (...)

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。  所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。  有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK v.02.xx 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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模擬型號

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL 模型
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模擬型號

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS 模型
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模擬型號

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - 熱模型
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模擬型號

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - 功率模型
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI 模型
lock = 需要匯出核准 (1 分鐘)
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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參考設計

TIDEP0026 — K2E 時鐘產生參考設計

單一時脈來源不應用於驅動高性能處理器裝置（例如基於多核心 ARM Cortex-A15 的 66AK2Ex 與 AM5K2Ex 處理器）的多個時脈輸入，因為過度的負載、反射與雜訊會對性能產生負面影響。透過使用差動時脈樹取代單一時脈來源，可避免這些情況發生。此設計展示了透過使用差動時脈樹，為 KeyStone II ARM A15 + DSP 與純 ARM 多核心處理器的 66AK2Ex 與 AM5K2Ex 系列產生時脈。此設計顯示了一個完整的時脈樹，可產生 SoC 核心與介面所需的所有時脈。

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參考設計

TIDEP0031 — 使用具有 PMBus 的 UCD9090 為 K2E 進行電源排序

K2E 裝置要求電源供應器按照正確順序進行排序。此設計展示了使用 UCD9090 為 KeyStone II ARM+DSP 的 66AK2Ex 和 AM5K2Ex 系列及純 ARM 多核心處理器的電源排序。UCD9090 是一款 10 軌 PMBus/I2C 可定址電源供應序列器和監控器。UCD9090 提供電源供應器啟用的順序和時序。此設計顯示 K2E EVM 平台專屬的電源排序實作。

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參考設計

TIDEP0041 — 可產生 AVS SmartReflex 核心電壓、適用於 K2E 的 PMBus 參考設計

K2E 需要對 CVDD 核心電壓使用 AVS SmartReflex 控制。此設計提供一種無須任何軟體即可產生適當電壓的方法。此電路目前實作於 XEVMK2EX。

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參考設計

TIDEP0042 — 使用 TPS544C25 和 PMBus 為 K2E 產生 AVS SmartReflex 核心電壓的參考設計

K2E 需要對 CVDD 核心電壓使用 AVS SmartReflex 控制。此設計提供使用 TPS544C25 軟體和 PMBus 介面產生適當電壓的方法。此電路可在 XEVMK2EX 上實作。

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